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data sheet n8954dsc april 7, 1999 BT8954 voice pair gain framer the BT8954 framer has been tailored specifically to meet the needs of voice pair gain systems (also referred to as ?cable relief systems? and ?digital subscriber line carriers?) by providing a direct connection to the dsl modem and the codec. it performs data, clock, and format conversions necessary to construct a pulse code multiplexed (pcm) channel from a symmetrical digital subscriber line (sdsl) or a high-bit-rate digital subscriber line (hdsl) channel. the pcm channel consists of transmit and receive data, clock, and frame sync signals configured for 2?18 voice channels. the pcm channel connects directly to popular pcm codecs. the digital subscriber line (dsl) channel interface consists of serial data and clock connected to a rs8973, bt8970 or a bt8960 dsl transceiver. the BT8954 supports clear and compressed voice system. when coupled with a bt8960, the BT8954 provides pcm4 functions at greater than 5 km reach with no voice compression, allowing v.34 modem operation. at one end, BT8954 multiplexes payload data from several pcm codecs with the appropriate overhead and signaling bits into one transport frame that is passed on to the bit-pump, for transport over a single twisted pair. at the other end, BT8954 demultiplexes the dsl bit stream into payload data sent to the pcm codec, and overhead data written into microcomputer-accessible registers. embedded operations channel (eoc) and signaling overhead can be inserted via the microcomputer interface (mci). control and status registers are accessed via the mci. one common register group configures the pcm interface formatter, phase-locked loop (pll), and pcm loopback (lb). another group of dsl channel registers configures the elastic store fifos, overhead muxes, receive framer, payload mapper, and the dsl loopback. status registers monitor received overhead, pll, fifo, and framer operations, including crc and febe error counts. functional block diagram 2b1q decoder 2b1q encoder lb pcm formatter microcomputer receive framer payload demux registers payload mux oh/signaling pcm rfifo pcm tfifo adpcm/pcm codecs microcomputer interface lb pll dsl bit pump rdat tdat hclk qclk pcmr pcmclk pcmf[18:1] pcmt bclk adpcmck distinguishing features voice pair gain framer ? frames and transports pcm data streams over 12?18,000 ft. (3.7?5.5 km) distances when coupled with bt8960 or bt8970 pcm interface ? supports popular pcm codecs ? programmable payload to support 2?18 64 kbps voice channels ? 2.048, 1.536 mhz pcm reference clock generation ? 6.144, 8.192, 20.48 mhz adpcm reference clock generation dsl interface ? connects to bt8960 or bt8970 ? supports 160?1168 kbps bit rates ? error performance monitoring ? auto tip/ring reversal microcomputer interface ? glueless interface to intel 8051 and motorola 68302 processors ? access to overhead and signaling registers supports adpcm codecs (32 kbps) pcm and dsl loopbacks cmos technology, 5 v operation low-power operation ? enables compatibility with line-powered systems 68-pin plcc jtag/ieee std 1149.1-1990 ?40 c to +85 c operation applications voice pair gain systems (clear) ? pcm2, pcm4(pcm1+3), pcm6, ? pcm8, pcm10/11, pcm12, pcm18 adpcm voice pair gain systems (compressed) ? adpcm12, adpcm24, adpcm36
n8954dsc conexant information provided by conexant systems, inc. (conexant) is believed to be accurate and reliable. however, no responsibility i s assumed by conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use . no license is granted by implication or otherwise under any patent rights of conexant other than for circuitry embodied in conexan t products. conexant reserves the right to change circuitry at any time without notice. this document is subject to change withou t notice. conexant and ?what?s next in communications technologies? are trademarks of conexant systems, inc. product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. all other marks mentioned herein are the property of their respective holders. ? 1999 conexant systems, inc. printed in u.s.a. all rights reserved reader response: to improve the quality of our publications, we welcome your feedback. please send comments or suggestions via e-mail to conexant reader response@conexant.com . sorry, we can't answer your technical questions at this address. please contact your local conexant sales office or local field applications engineer if you have technical questions. ordering information model number package ambient temperature BT8954 68-pin plastic leaded chip carrier (plcc) ? 40 c to +85 c
n8954dsc conexant iii table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1.0 dsl systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 voice pair gain applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.1 repeaters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.2 subscriber modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2 system interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 2.0 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3.0 circuit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 dsl frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.1 detailed frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.2 differences between the dsl and hdsl t1/e1 frame formats . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.2.1 extra_z_bit option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.3 overhead bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.1 2b1q decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.2 receive framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.3.3 crc check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3.4 descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.5 payload demux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.1 oh/signaling registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.2 transmit signaling fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.4.3 payload mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.4.4 crc calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.4.5 scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.4.6 2b1q encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
table of contents BT8954 voice pair gain framer iv conexant n8954dsc 3.5 pcm formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.6 loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.7 synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.7.1 cotf transmitter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.7.2 rtf receiver synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.7.3 rtf transmitter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.7.4 cotf receiver synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.7.5 round trip delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.8 microcomputer interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.8.1 microcomputer read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.8.1.1 multiplexed address/data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.8.1.2 separated address/data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.8.2 interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.8.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.9 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 4.0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 register types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 register groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.3 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.4 transmitter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 0x80, 0x81 ? transmit embedded operations channel (teoc_lo, teoc_hi) . . . . . . . . . . 4-4 0x82, 0x83 ? transmit indicator bits (tind_lo, tind_hi) . . . . . . . . . . . . . . . . . . . . . . . . 4-4 0x84 ? transmit signaling fifos (tsfifo_i, tsfifo_o) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 0x85 ? transmit fifo water level (tfifo_wl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 0x86 ? transmit command register 1 (tcmd_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 0x87 ? transmit command register 2 (tcmd_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.5 receiver registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 0x90 ? receive command register 1 (rcmd_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 0x91 ? receive command register 2 (rcmd_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.6 dsl channel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 0xa0 ? dsl frame length (dframe_len) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 0xa1 ? sync word (sync_word) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 0xa2, 0xa3 ? rx fifo water level (rfifo_wl_lo, rfifo_wl_hi) . . . . . . . . . . . . . . . . 4-13 4.7 pll configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 0xb0 ? pll_int register (pll_int) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 0xb1 ? pll_frac_hi register (pll_frac_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 0xb2 ? pll_frac_lo register (pll_frac_lo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 0xb3 ? pll_a register (pll_a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 0xb4 ? pll_b register (pll_b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 0xb5 ? pll_scale register (pll_scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
BT8954 table of contents voice pair gain framer n8954dsc conexant v 4.8 common . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 0xc0 ? command register 1 (cmd_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 0xc1 ? revision identification (rev_id) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4.9 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 0xd0 ? interrupt status register (isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 0xd1 ? interrupt mask register (imr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4.10 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 0xd3 ? scrambler reset (scr_rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 0xd4 ? transmit fifo reset (tfifo_rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 0xd5 ? reset pointer to transmit signaling fifos (tsfifo_ptr_rst) . . . . . . . . . . . . . . 4-20 0xd6 ? reset pointer to receive signaling fifos (rsfifo_ptr_rst) . . . . . . . . . . . . . . 4-20 0xd7 ? receive elastic store fifo reset (rfifo_rst) . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 0xd8 ? receive framer synchronization reset (sync_rst) . . . . . . . . . . . . . . . . . . . . . 4-21 0xd9 ? error count reset (err_rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 0xda ? reset receiver (rx_rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 0xdb ? update tsfifo_o (update_tsfifo_o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 0xdc ? update rsfifo_o (update_rsfifo_o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4.11 receive/transmit status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 0xe0, 0xe1 ? receive embedded operations channel (reoc_lo, reoc_hi) . . . . . . . . . 4-22 0xe2, 0xe3 ? receive indicator bits (rind_lo, rind_hi) . . . . . . . . . . . . . . . . . . . . . . . 4-22 0xe4 ? receive signaling fifos (rsfifos) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 0xe5 ? receive status 1 (rstatus_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 0xe6 ? receive status 2 (rstatus_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 0xe7 ? transmit status 1 (tstatus_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 0xe8 ? crc error count (crc_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 0xe9 ? far end block error count (febe_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 4.12 pcm formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 0xf0 ? pcm frame length (pframe_len) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 0xf1 ? pcm format (pcm_format1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 5.0 electrical and mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.4 dsl interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.5 pcm interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.1.6 microcomputer interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.1.7 test and diagnostic interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.2 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
table of contents BT8954 voice pair gain framer vi conexant n8954dsc appendix a: applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.1 interfacing to the bt8960/bt8970 hdsl transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.2 interfacing to the texas instrument tp3054a pcm codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 a.3 interfacing to the motorola 68302 16-bit processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.4 interfacing to the intel 8051 8-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 a.5 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4
BT8954 list of figures voice pair gain framer n8954dsc conexant vii list of figures figure 1-1. block diagram of a pcm4 voice pair gain modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 figure 1-2. repeater block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 figure 1-3. subscriber modem (terminal) system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 figure 1-4. BT8954 system interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 figure 2-1. pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 figure 2-2. BT8954 functional pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 figure 3-1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 figure 3-2. basic dsl frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 figure 3-3. receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 figure 3-4. receive framer finite state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6 figure 3-5. threshold correlation effect on expected sync locations . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 figure 3-6. lfsr structure for transmission in the remote central office direction. . . . . . . . . . . . 3-8 figure 3-7. lfsr structure for transmission in the central office remote direction. . . . . . . . . . . . 3-8 figure 3-8. transmitter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 figure 3-9. double buffering, using transmit s-bits registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 figure 3-10. lfsr structure for transmission in the remote central office direction. . . . . . . . . . . 3-12 figure 3-11. lfsr structure for transmission in the central office remote direction. . . . . . . . . . . 3-13 figure 3-12. pcm formatter detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 figure 3-13. pcmf [18:1] waveforms for encoded and decoded frame sync modes. . . . . . . . . . . . . 3-15 figure 3-14. pcm and dsl loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 figure 3-15. cotf and rtf synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17 figure 3-16. cotf transmitter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17 figure 3-17. rtf receiver synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 figure 3-18. rtf transmitter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18 figure 3-19. cotf receiver synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 figure 3-20. mci port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 figure 3-21. functional diagram of the read and write controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 figure 3-22. interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 figure 3-23. functional diagram of the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 figure 4-1. transmit signaling fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 figure 4-2. example of three signaling bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 figure 4-3. receive signaling fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 figure 4-4. example of three signaling bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
list of figures BT8954 voice pair gain framer viii conexant n8954dsc figure 5-1. qclk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 figure 5-2. dsl interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 figure 5-3. pcm interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 figure 5-4. mci write timing, intel mode (motel = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 figure 5-5. mci write timing, motorola mode (motel = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 figure 5-6. mci read timing, intel mode (motel = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 figure 5-7. mci read timing, motorola mode (motel = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 figure 5-8. internal write timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 figure 5-9. jtag interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 figure 5-10. input waveforms for timing tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10 figure 5-11. output waveforms for timing tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -10 figure 5-12. output waveforms for three-state enable and disable tests . . . . . . . . . . . . . . . . . . . . . . 5-10 figure 5-13. 68-pin plcc package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-11 figure a-1. BT8954 to bt8960/bt8970 dsl transceiver interconnection . . . . . . . . . . . . . . . . . . . . . . . . a-1 figure a-2. BT8954 to texas instrument tp3054a pcm codec interconnection . . . . . . . . . . . . . . . . . . a-2 figure a-3. BT8954 to motorola 68302 processor interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 figure a-4. BT8954 to intel 8051 controller interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4
BT8954 list of tables voice pair gain framer n8954dsc conexant ix list of tables table 2-1. hardware signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 table 3-1. dsl frame structure and overhead bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 table 3-2. 2b1q decoder alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 table 3-3. 2b1q encoder alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 table 3-4. pcm and dsl loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16 table 3-5. pll_x register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 table 3-6. pll_c register bit representation of pll_w and pll_y . . . . . . . . . . . . . . . . . . . . . . . . 3-26 table 3-7. pll_p register bit representation of p_factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 table 3-8. factors for fpll = 196.608 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-27 table 3-9. factors for fpll = 204.800 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-28 table 4-1. address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 table 4-2. transmitter register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 table 4-3. dsl receive write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 table 4-4. dsl channel configuration write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 table 4-5. pll configuration write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-14 table 4-6. common command write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 table 4-7. interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 table 4-8. reset write registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 table 4-9. receive and transmit status read registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 table 4-10. pcm formatter register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 28 table 5-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 table 5-2. recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 1 table 5-3. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 table 5-4. qclk timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 table 5-5. dsl interface switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 table 5-6. pcm interface switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 table 5-7. microcomputer interface timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 table 5-8. microcomputer interface switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 table 5-9. test and diagnostic interface timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 table 5-10. test and diagnostic interface switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
list of tables BT8954 voice pair gain framer x conexant n8954dsc
n8954dsc conexant 1-1 1 1.0 dsl systems 1.1 voice pair gain applications a well-established market exists for voice pair gain systems. in such systems, several simultaneous phone conversations are transported over a single twisted pair. these systems are used by telecommunications service providers to maximize the utilization of the existing copper plant and allow it to provision many more telephone circuits than is possible with ordinary 4 khz analog transport. the external interfaces of voice pair gain systems, at both the central office and remote ends, are analog pots lines. two carrier techniques facilitate single pair gain transmission: frequency domain multiplexed systems (fdm) and time domain multiplexed systems (tdm). in fdm systems each voice channel is modulated by a successively higher carrier such that the composite transmission consists of several frequency bands. in tdm systems the voice data is digitized and sampled in a channel-multiplexed fashion. although fdm systems are currently fielded, recent trends are clearly toward tdm systems because of the inherent advantages associated with digital transmission. traditional pcm4 (also called ?1+3?) voice pair gain systems use a combination of 2:1 adaptive differential pulse code modulation (adpcm) compression and basic rate integrated service digital network (isdn) u-interface devices to transport four-voice conversations on one twisted pair. the disadvantage of this scheme is that clear 64 kbps channel capacity is lost due to the adpcm voice compression algorithm. this may prevent high-speed facsimile and data transmissions from being transported reliably. since telecommunication service providers want to provision telephone equipment that can be used for business purposes, this disadvantage has caused them to seek alternative solutions that can handle data as well as voice. when used with a digital subscriber line (dsl) bit pump, such as the bt8960, pcm4 systems can be constructed to transmit clear 64 kbps channels, thereby enabling voice, fax, and data transmission. the BT8954 with a higher speed dsl bit pump, such as the bt8970, allows a greater number of voice conversations to be simultaneously carried over a single twisted pair. the BT8954/bt8970 combination can facilitate up to 18 64-kbps time slots. if clear channel capability is needed, this combination results in up to 18 (pcm18) systems. when used with 2:1 adpcm voice compression, the BT8954/bt8970 combination makes up to 36 voice channels possible.
1.0 dsl systems BT8954 1.1 voice pair gain applications voice pair gain framer 1-2 conexant n8954dsc BT8954 ? s position among the key elements of a pcm4 (4-channel) voice pair gain modem is illustrated in figure 1-1 . the pulse code multiplexed (pcm) codec and subscriber line interface circuit (slic) chips for each channel perform the transmit encoding (a/d conversion) and receive decoding (d/a conversion) of voice signals. the time-division multiplexing of the voice signals on the pcmt and pcmr serial buses is as follows: BT8954 informs pcm codec_n with the pcmfn frame sync when to expect the next byte from BT8954 on the pcmr bus, and when to put its next byte on the pcmt bus. in this way, BT8954 uses the pcmfn frame sync to designate the time slot that codec_n has access to the pcmr and pcmt buses. 1.1.1 repeaters figure 1-2 illustrates a pair of BT8954 repeaters placed in line between central office and remote terminals to extend the transmission distance. for each BT8954 repeater, the bclk/qclk is connected to the bclk/qclk of its source transceiver while the bclk_rep/qclk_rep is connected to the bclk/qclk of its destination transceiver. the central office BT8954 gets its hclk/bclk/qclk from the central office transceiver, which generates them from a free-running crystal. the repeater transceiver connected to the central office recovers its hclk, bclk, and qclk from the hdsl line. these signals then drive the hclk, bclk, and qclk pins of the central office to remote terminal BT8954, and the hclk, bclk_rep, and qclk_rep pins of the remote terminal to central office BT8954. the repeater transceiver connected to the remote terminal receives hclk from the repeater transceiver connected to the central office. the repeater transceiver connected to the remote terminal generates bclk/qclk and drives the bclk/qclk pins of the remote terminal to central office terminal BT8954. the repeater transceiver drives the bclk_rep/qclk_rep pins of the central office terminal to remote terminal BT8954. in repeater mode, the BT8954 does not use the fifos. first, data received from the bit pump is descrambled. figure 1-1. block diagram of a pcm4 voice pair gain modem . bt8960/70 bit pump hybrid qclk bclk rdat tdat pcmclk pcmr pcmt pcmf1 pcmf4 codec1 fsx1/fsr1 c1 c2 det* e0 BT8954 vpg framer slic1 c1 c2 det* e0 slic4 codec4 fsx4/fsr4 microcomputer logic
BT8954 1.0 dsl systems voice pair gain framer 1.1 voice pair gain applications n8954dsc conexant 1-3 next, eoc and ind overhead are inserted from the BT8954 eoc and ind registers. the crc is then calculated and inserted. then the data is scrambled and transmitted to the destination bit pump. BT8954 (c r) scrambles like BT8954 in the central office terminal but descrambles like BT8954 in the remote terminal. that is, scram_tap = 0 [tcmd2; 0x87.1] but dscram_tap = 1 [rcmd_2; 0x91.4]. BT8954 (r c) scrambles like BT8954 in the remote terminal but descrambles like BT8954 in the central office terminal. that is, scram_tap = 1 [tdmd2; 0x87.1] but dscram_tap = 0 [rcmd_2; 0x91.4]. figure 1-2. repeater block diagram tdat rdat bt8960/ rdat tdat bt8970 bt8960/ bt8970 BT8954 BT8954 (c r) central office terminal repeater bclk qclk bclk_rep qclk_rep bclk_rep hclk rdat tdat bt8960/ bt8970 BT8954 remote terminal bclk BT8954 (r c) tdat qclk_rep rdat qclk xtal bt8960/ bt8970 xtal xtal
1.0 dsl systems BT8954 1.1 voice pair gain applications voice pair gain framer 1-4 conexant n8954dsc 1.1.2 subscriber modem figure 1-3 illustrates a dsl data modem application where a central processing unit (cpu) delivers pcm data directly to BT8954. alternatively, a multichannel communications controller such as bt8472/4 can be used to manage the transfer of data between the cpu and the pcm channel through a local shared memory. figure 1-3. subscriber modem (terminal) system block diagram single channel payload BT8954 bit pump cpu memory pcm serial port BT8954 pcm bt8472/4 hdlc controller cpu shared multichannel payload memory pci bit pump codec pots
BT8954 1.0 dsl systems voice pair gain framer 1.2 system interfaces n8954dsc conexant 1-5 1.2 system interfaces system interfaces and associated signals for the BT8954 functional circuit blocks are illustrated in figure 1-4 . circuit blocks are described in the following sections, and signals are defined in table 2-1 . figure 1-4. BT8954 system interfaces hclk pcmt pcmcko pcmr pcmf[18:1] irq* rst* bclk qclk tdat rdat ad[7:0] cs* ale rd*/ds* wr*/r/w* pcm interface dsl interface microcomputer interface pll tck tdi tdo tms te s t access addr[7:0] motel* muxed adpcmck pcmcki qclk_rep bclk_rep
1.0 dsl systems BT8954 1.2 system interfaces voice pair gain framer 1-6 conexant n8954dsc
n8954dsc conexant 2-1 2 2.0 pin descriptions BT8954 pin assignments for the 68-pin plastic leaded chip carrier (plcc) package are illustrated in figure 2-1 . the functional pinout for the BT8954 is illustrated in figure 2-2 , and the signals are defined in table 2-1 . figure 2-1. pin diagram gnd adpcmck pcmf[13] pcmf[12] pcmf[11] pcmf[10] pcmf[9] vdd gnd pcmf[8] pcmf[7] pcmf[6]/epcmf[6] pcmf[5]/epcmf[5] pcmf[4]/epcmf[4] pcmf[3]/epcmf[3] pcmf[2]/epcmf[2] pcmf[1]/epcmf[1] qclk qclk_rep rd*/ds* wr*/r/w* ale addr[6] addr[5] addr[4] addr[3] addr[2] addr[1] addr[0] irq* gnd vdd pcmcko pcmcki pcmr pcmf[14] pcmf[15] pcmf[16] pcmf[17] pll_gnd pll_vdd pcmf[18] tdat rdat bclk bclk_rep hclk dtest pcmt tms tdi tdo tck rst* muxed motel* ad[0] ad[1] ad[2] ad[3] ad[4] ad[5] ad[6] ad[7] vdd 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 61 62 63 64 65 66 67 68 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 BT8954 cs* vdd gnd
2.0 pin descriptions BT8954 voice pair gain framer 2-2 conexant n8954dsc figure 2-2. BT8954 functional pinout addr[6:0] address bus i 16, 19-24 65-68,3 motel* wr*/r/w* ale muxed ad[7:0] rst* motorola/intel write*/read/write address latch enable interrupt request address data reset microcomputer interface bclk dsl interface bclk_rep qclk_rep bclk repeater qclk repeater pcmcko adpcmck pcmt pcmcki pcm clock output adpcm clock output pcm frame sync pcm transmit data input pcm clock input pcm interface test and diagnostic interface tdi tms tdo jtag test data out jtag test data in jtag test mode select tdat bit clock o repeater pins i i i i i/o i i i o o o o i i i i 59 4 6 63 7 11 15 37 14 28-35 36 38 40 41 42 43 44-51 62 i = input, o = output, quaternary clock receive data pcmr 64 tck jtag test clock pcm receive data output cs* rd*/ds* chip select read/data strobe i i 12 13 i i i 10 5 transmit data o 54-58 epcmfn[6:1] hclk 8 hclk input i pll 39 i i/o = bidirectional, od = open drain qclk rdat 44-49 irq* interrupt request od 25 pcmf[18:1] pcm frame sync o gnd_o 26, 60 ground dtest 9 digital test i power and ground vdd vdd power supply power supply 61, 27 17, 53 pll_vdd pll power supply 2 pll_gnd pll ground 1 gnd_ic 18, 52 ground i
BT8954 2.0 pin descriptions voice pair gain framer n8954dsc conexant 2-3 table 2-1. hardware signal definitions (1 of 4) pin label pin number signal name i/o definition microcomputer interface (mci) motel* 36 motorola/intel* i selects between motorola and intel handshake conventions for the rd*/ds* and wr*/r/w* signals. motel* = 1 for motorola protocol: ds*, r/w*; motel* = 0 for intel protocol: rd*, wr*. ale 15 address latch enable i falling-edge-sensitive input. the value of ad[7:0] when muxed = 1, or of addr[7:0] when muxed = 0, is internally latched on the falling edge of ale. cs* 12 chip select i active-low input used to enable read/write operations on the microcomputer interface (mci). rd*/ds* 13 read/data strobe i bimodal input for controlling read/write access on the mci. when motel* = 1 and cs* = 0, rd*/ds* behaves as an active-low data strobe, ds*. internal data is output on ad[7:0] when ds* = 0 and r/w* = 1. external data is internally latched from ad[7:0] on the rising edge of ds* when r/w* = 0. when motel* = 0 and cs* = 0, rd*/ds* behaves as an active-low read strobe rd*. internal data is output on ad[7:0] when rd* = 0. write operations are not controlled by rd* in this mode. wr*/r/w* 14 write/read/write i bimodal input for controlling read/write access on the mci. when motel* = 1 and cs* = 0, wr*/r/w* behaves as a read/write select line, r/w*. internal data is output on ad[7:0] when ds* = 0 and r/w* = 1. external data is internally latched from ad[7:0] on the rising edge of ds* when r/w* = 0. when motel* = 0 and cs* = 0, wr*/r/w* behaves as an active-low write strobe, wr*. external data is internally latched from ad[7:0] on the rising edge of wr*. read operations are not controlled by wr* in this mode. ad[7:0] 28 ? 35 address-data[7:0] i/o eight-bit bidirectional multiplexed address-data bus. ad[7] = msb, ad[0] = lsb. usage is controlled using the muxed signal. addr[6:0] 19 ? 24, 16 address bus [6:0] (not multiplexed) i provides a glueless interface to microcomputers with separate address and data buses. addr[6] = msb, addr[0] = lsb. usage is controlled using the muxed signal. muxed 37 addressing mode select i controls the mci addressing mode. when muxed = 1, the mci uses ad[7:0] as a multiplexed signal for address and data (typical of intel processors). when muxed = 0, the mci uses addr[7:0] as the address input and ad[7:0] for data only (typical of motorola processors). irq* 25 interrupt request o, od active-low open-drain output that indicate requests for interrupt. asserted whenever at least one unmasked interrupt flag is set. remains inactive whenever no unmasked interrupt flags are present. rst* 38 reset i asynchronous, active-low, level-sensitive input that resets the framer.
2.0 pin descriptions BT8954 voice pair gain framer 2-4 conexant n8954dsc dsl interface bclk 6 bit clock i corresponds to the dsl channel. bclk operates at the 2b1q symbol rate. the rising edge of bclk outputs 2x tdat. the falling edge of bclk samples qclk at the rdat input. (in the repeater terminal, bclk is the bclk from the bit pump to which rdat is connected.) note(s): refer to appendix a, page 81. the bclk signal from the bit-pump to the channel unit device is sensitive to overshoot and undershoot. the bclk sensitivity could cause bit-errors in the system. a 100 ? series terminating resistor might be required to help dampen the overshoot and undershoot. the bit-pump line cards include a 74hct244 to drive the long traces through the motherboard 96-pin connectors. qclk 10 quaternary clock i operates at the 2b1q symbol rate (1/2 bit rate) and identifies sign and magnitude alignment of both the rdat and tdat serially encoded bit streams. the falling edge of bclk samples qclk: 0 = sign bit; 1 = magnitude bit. in the repeater terminal, bclk is the bclk from the bit pump to which rdat is connected. tdat 4 transmit data o dsl transmit data output at the bit rate on the rising edge of bclk. serially encoded with the 2b1q sign bit aligned to the qclk low level and the 2b1q magnitude bit aligned to the qclk high level. rdat 5 receive data i dsl receive data input sampled on the falling edge of bclk. the serially encoded 2b1q sign bit is sampled when qclk is low, and the 2b1q magnitude bit is sampled when qclk is high. repeater pins bclk_rep 7 bclk from destination bit pump in a repeater terminal i bclk from the bit pump to which the BT8954 tdat is connected in a repeater terminal. it is used only in the repeater mode and should be tied to vdd or gnd in non-repeater terminals. qclk_rep 11 qclk from destination bit pump in a repeater terminal i qclk from the bit pump to which the BT8954 tdat is connected in a repeater terminal. it is used only in the repeater mode and should be tied to vdd or gnd in non-repeater terminals. table 2-1. hardware signal definitions (2 of 4) pin label pin number signal name i/o definition
BT8954 2.0 pin descriptions voice pair gain framer n8954dsc conexant 2-5 pcm interface pcmcko 62 pcm clock output o output pcm clock for sending and receiving bits from pcm codecs. it is generated by the pll and is 1.536 mhz or 2.048 mhz depending on the pll configuration. connect to receive/transmit bit clocks and receive/transmit master clocks of pcm codecs. in normal operation, tie to pcmcki. pcmcki 63 pcm clock input i sends and receives bits from pcm codecs. controls the pcm formatter, reads from the rfifo, and writes into the tfifo. in normal operation, tie to pcmcko. adpcmck 59 adpcm clock output o used by adpcm chips. it is 10x or 4x pcmcko. pcmfn 3, 44-51, 54-58, 65-68 pcm frame sync (n = 1,...,18) o frame sync pulse for receiving bits from and transmitting bits to a pcm codec. connect to receive/transmit frame syncs of the pcm codec. this signal is low if not connected to any pcm codec. it supports both short-frame and long-frame operations. epcmfn 44-49 encoded pcm frame sync (n = 1,...,6) o channel number of bits received from and transmitted to pcm codecs. connect to a decoder to generate receive/transmit frame syncs for pcm codecs. for n = 1,..,6, epcmfn is multiplexed with pcmfn depending on the enc_fsync configuration in the pcm format register [pcm_format; 0xf1.6]. pcmr 64 pcm receive data output o serial bit stream to pcm codecs is shifted out at the rising edge of pcmcki. pcmt 43 pcm transmit data input i serial bit stream from the pcm codecs is sampled at the falling edge of pcmcki. pll hclk 8 hclk input i connects to the hclk output of the bt8960/70 bit pump. it is 32xbclk or 64xqclk and is used as the pll clock reference. dtest 9 digital test i dtest ? active high test input used by conexant to enable an internal test mode. this input should be tied to ground (gnd). table 2-1. hardware signal definitions (3 of 4) pin label pin number signal name i/o definition
2.0 pin descriptions BT8954 voice pair gain framer 2-6 conexant n8954dsc test and diagnostic interface tdi 41 jtag test data input i test data input per ieee std 1149.1-1990. used for loading all serial instructions and data into internal test logic. sampled on the rising edge of tck. tdi can be left unconnected if it is not being used because it is pulled up internally. tms 42 jtag test mode select i test mode select input per ieee std 1149.1-1990. internally pulled-up input signal that controls the test-logic state machine. sampled on the rising edge of tck. tms can be left unconnected if it is not being used because it is pulled up internally. tdo 40 jtag test data output o test data output per ieee std 1149.1-1990. three-state output used for reading all serial configuration and test data from internal test logic. updated on the falling edge of tck. tck 39 jtag test clock i test clock input per ieee std 1149.1-1990. used for all test interface and internal test-logic operations. if unused, tck should be pulled low. power and ground vdd 17, 27, 53, 61 power supply i power supply pins for the i/o buffers and core logic functions. 5vdc 5%. gnd 18, 26, 52, 60 ground g ground pins for the i/o buffers and core logic functions. must be held at the same potential as pll_gnd. pll_vdd 2 pll power supply p dedicated supply pin for the pll circuitry. connect to vdd externally. pll_gnd 1 pll ground g dedicated ground pin for the pll circuitry. must be held at the same potential as gnd. table 2-1. hardware signal definitions (4 of 4) pin label pin number signal name i/o definition
n8954dsc conexant 3-1 3 3.0 circuit descriptions 3.1 overview figure 3-1 details the major blocks and pins of BT8954. after the 2b1q decode of the bit stream is received from the dsl bit pump, the receive framer detects the beginning of the digital subscriber line (dsl) frame, and generates the required pulses for synchronizing the different demultiplexing functions. the payload demux block strips overhead bits from the dsl frame and puts the payload for the different pulse code multiplexed (pcm) time slots into the pcm rfifo. the pcm rfifo is emptied through the pcmr pin. on the transmit side, the pcm tfifo is filled with serial data on pcmt. payload data from the tfifo is multiplexed with signaling data from the signaling registers and overhead from the oh (overhead) registers. the multiplexed data is then sent to the dsl bit pump, through the tdat pin, after being 2b1q encoded. pcm and dsl loopback functions are performed using the loopback blocks. the pcmclk, adpcmck, and the internal clock are generated and synchronized to bclk with the pll. the pll uses hclk as its clock reference. figure 3-1. block diagram 2b1q decoder 2b1q encoder lb pcm formatter microcomputer receive framer payload demux payload mux pcm rfifo pcm tfifo adpcm/pcm codecs lb pll dsl bit-pump rdat tdat bclk hclk pcmr pcmclk pcmf[18:1] pcmt transmitter receiver adpcmck qclk oh/signaling registers rst* irq* motel* cs* wr/rw* ale muxed ad[7:0] addr[7:0] microcomputer interface ds*
3.0 circuit descriptions BT8954 3.2 dsl frame format voice pair gain framer 3-2 conexant n8954dsc 3.2 dsl frame format the dsl frame is the fundamental data element of the bit streams transmitted and received by BT8954 at the dsl interface. it is patterned after the 2 t1, 2 e1, and 3 e1 frame structures. figure 3-2 illustrates the basic format of a dsl frame. 3.2.1 detailed frame structure each frame has a 6 ms duration and is made up of 48 payload blocks. each block contains s number of s-bits (for data signaling) and n number of bytes where n is the number of pcm time slots. the microcomputer selects the number of s-bits in the num_sbits [3:0] field of transmit command register 2 [tcmd_2; 0x87.5:2] and the n number of pcm time slots in the num_ chan[4:0] field of the pcm format register [pcm_format; 0xf1.4:0]. s-bits vary from 0 to 8 bits, while n varies from 1 to 18 time slots. groups of 12 payload blocks are concatenated, and each group is separated by an ordered set of doh (dsl overhead) bits. a 14-bit sync word pattern identifies the beginning of the dsl frame. forty-eight overhead bits are defined in one dsl frame with the last 2 bits used for stuffing. this corresponds to an 8 kbps (48 bits/6 ms) overhead bit rate. the 2 bits of stuffing are the average number of stuffing bits per frame since the transmitter alternatively transmits 0 bits of stuffing or 4 bits of stuffing in each frame. figure 3-2. basic dsl frame format sync word d o h b 0 1 b 0 2 b 1 2 d o h b 1 3 b 1 4 b 2 4 d o h b 2 5 b 2 6 b 3 6 d o h b 3 7 b 3 8 sync word s-bits byte1 byte2 byte3 byte_n 6 ms ? 6+ ? ? 6- ? 0 ms 1/(32n + 4s + 4) ms bnn 0-8 bits 8 bits 7q 1q 12x(4n+0.5s) 5q 5q 5q legend: bnn = payload blocks 1-48 doh = dsl overhead dsl frame s-bits = data signaling bits #quats = (4n + 0.5s) #bits = 2 x (4n + 0.5s) #quats = 4 x (48n + 6s) + 24 = 192n + 24s + 24 #bits = 2 x (192n + 24s + 24) bit rate (kbps) = 2 x (192n + 24s + 24) = (64n + 8s + 8) 6 ms n = # of voice channels b 4 8 1q 1q s t q 1 s t q 2 s t q 1 s t q 2
BT8954 3.0 circuit descriptions voice pair gain framer 3.2 dsl frame format n8954dsc conexant 3-3 3.2.2 differences between the dsl and hdsl t1/e1 frame formats the dsl frame format is similar to the t1/e1 frame formats that are transported on one hdsl loop. the main difference is due to the number of s-bits. while fixed as 1 f-bit/block and 1 z-bit/block for the t1 and e1 hdsl frame formats, it can vary between 0 and 8 bits for the dsl frame format. the number of s-bits is allowed to vary up to 8 bits so that a variable number of d-channel bit rates (up to 64 kbps) can be supported. 3.2.2.1 extra_z_bit option some systems (e.g., pcm11) require an extra 8 kbps z-bit field in addition to the basic frame structure outlined in figure 3-2 . to accommodate such systems, each block of the dsl frame has an extra z-bit (preceding the s-bits field) that can be enabled for transmit when extra_z_bit in command register 1 [cmd_1; 0xc0.5] is set. for example, a pcm11 system can have a 784 kbps bit rate consisting of 704 kbps (11x64 kbps) of payload, 8 kbps of overhead, 64 kbps of signaling information, and 8 kbps of the extra z-bit. this extra z-bit field is a dummy field and is not accessible through the mc. 3.2.3 overhead bit allocation the overhead bit allocation of the dsl frame is the same as that of the hdsl frame given in table 3-1 . table 3-1. dsl frame structure and overhead bit allocation (1 of 2) doh bit number symbol bit name doh register bit 1 ? 14 sw1 ? sw14 sync word ? 15 losd loss of signal ind[12] 16 febe far end block error ind[11] payload blocks 1 ? 12 17 ? 20 eoc1 ? eoc4 embedded operations channel eoc[12] ? eoc[9] 21 ? 22 crc1 ? crc2 cyclic redundancy check ? 23 ps1 htu-r power status ind[10] 24 ps2 power status bit 2 ind[9] 25 bpv bipolar violation ind[8] 26 eoc5 embedded operations channel eoc[8] payload blocks 13 ? 24 27 ? 30 eoc6 ? eoc9 embedded operations channel eoc[7] ? eoc[4] 31 ? 32 crc3 ? crc4 cyclic redundancy check ? 33 hrp hdsl repeater present ind[7] 34 rrbe repeater remote block error ind[6] 35 rcbe repeater central block error ind[5] 36 rega repeater alarm ind[4]
3.0 circuit descriptions BT8954 3.2 dsl frame format voice pair gain framer 3-4 conexant n8954dsc payload blocks 25 ? 36 37 ? 40 eoc10 ? eoc13 embedded operations channel eoc[3] ? eoc[0] 41 ? 42 crc5 ? crc6 cyclic redundancy check ? 43 rta remote terminal alarm ind[3] 44 rtr ready to receive ind[2] 45 uib unspecified indicator bit ind[1] 46 uib unspecified indicator bit ind[0] payload blocks 37 ? 48 table 3-1. dsl frame structure and overhead bit allocation (2 of 2) doh bit number symbol bit name doh register bit
BT8954 3.0 circuit descriptions voice pair gain framer 3.3 receiver n8954dsc conexant 3-5 3.3 receiver the receiver performs sync word detection, overhead extraction, descrambling of payload data, error performance monitoring, and payload mapping of dsl data from the received dsl frame into the pcm rfifo. figure 3-3 illustrates the receiver block diagram. the receiver consists of the 2b1q decoder, receive framer, descrambler, crc check, and payload demux. 3.3.1 2b1q decoder the 2 binary, 1 quaternary (2b1q) decoder provides the capability to connect directly to the bt8960/70 dsl transceivers. the 2b1q decoder samples and aligns the incoming sign and magnitude data. refer to table 3-2 for 2b1q mapping. figure 3-3. receiver block diagram state cnt sync detector crc chk 2b1q decoder descrambler bclk qclk rdat tdat rdsl_6ms pcm rfifo receive framer pd_loop 0 1 rdat_descr payload demux stuff detector table 3-2. 2b1q decoder alignment first bit (sign) second bit (magnitudes) quaternary symbol (quat) 10 +3 11 +1 01 ? 1 00 ? 3
3.0 circuit descriptions BT8954 3.3 receiver voice pair gain framer 3-6 conexant n8954dsc 3.3.2 receive framer the receive framer generates the rdsl_6ms pulse after detecting the sync word. rdsl_6ms generates pointers that control overhead extraction in the crc and oh demux circuitry. the mc initializes the framer to the out_of sync state by writing any data value to sync_rst [0xd8]. from the out_of sync state, the framer advances to sync_acquired when the sync word is detected. the framer searches all bits received on rdat to locate a match with the sync word pattern, sync_word [0xa1]. due to the possibility of tip/ring connector reversal, all sign bits received on rdat might be inverted. therefore, the receive framer searches for both the programmed sync word value and the sign-inverted sync word value. consequently, a maximum of two values of the sync word are used in finding the frame location. if the sync word detected is a sign-inverted version of the configured sync word, the framer sets the tip/ring inversion [tr_invert] status bit of the receive status 1 register [rstatus_1; 0xe5.6] and automatically inverts the sign of all quats received on rdat. after detecting the sync word and changing to the sync_acquired state, the framer progresses through a programmable number of intermediate sync_acquired states before entering the in_sync state. in each sync_acquired state, the framer searches for the previously detected sync word value in one of two locations based upon the absence or presence of the four stuff bits (detected by the stuff detector). if the sync word is detected in one of the two possible locations, the state_cnt[2:0] counter is incremented [rstatus_2; 0xe6.2:0]. when state_cnt[2:0] increments to the value selected by the reach_sync[2:0] criteria [rcmd_1; 0x90.2:0], the framer changes to the in_sync state. during the sync_acquired state, if valid sync is not detected at one of the two possible locations, the framer returns to the out_of_sync state as illustrated in figure 3-4 . figure 3-4. receive framer finite state machine sync consecutive sync_errored states per loss_sync criteria 87654321 8 7 6 5 4 3 2 1 no sync consecutive sync_acquired states per reach_sync criteria sync no sync sync no sync in_sync no sync sync out_of sync
BT8954 3.0 circuit descriptions voice pair gain framer 3.3 receiver n8954dsc conexant 3-7 after entering in_sync, the framer either remains in_sync as successive sync words are detected or regresses to the sync_errored state if sync pattern errors are found. during sync_errored states, the number of matching bits from each comparison of received sync word and the programmed sync word pattern must meet or exceed the programmed pattern match tolerance specified by thresh_corr [rcmd_2; 0x91.3:0]. if the number of matching bits falls below tolerance, the framer expands the locations searched to quats on either side of the expected location, as illustrated in figure 3-5 . after detecting a sync pattern error and changing to the sync_ errored state, the framer passes through a programmable number of intermediate sync_errored states, before entering the out_of sync state. state_cnt increments for each frame in which sync is not detected until the count reaches the loss_sync[2:0] criteria [rcmd_1; 0x90.5 ? 3] and the framer enters the out_of sync state. if at any time during the sync_errored state the framer detects a completely correct sync word pattern at one of the valid frame locations, then framer returns to the in_sync state. the etsi standard, for hdsl transport, recommends the reach_sync = 2 and loss_sync = 6 framing criteria. 3.3.3 crc check the crc check block calculates a crc value for every received dsl frame. the crc check block reports an error if the crc in the current frame (calculated at the other end ? s transmitter) does not match the crc that was calculated for the previous dsl receive frame. individual dsl block errors are reported in the crc_error bit of the receive status 2 register [rstatus_2; 0xe6.5] and accumulated in the crc error count register [crc_cnt; 0xe8]. the crc calculation in the receiver is exactly the same as that in the transmitter. figure 3-5. threshold correlation effect on expected sync locations sync_errored 1 sync_errored 2 sync_errored 3 6 ms 12 ms 18 ms 0 t ? 1q +1q ? 1q +1q ? 1q +1q sync_errored 1 sync_errored 2 sync_errored 3 6 ms 12 ms 18 ms 0 t ? 2q +2q ? 1q +1q ? 2q +2q ? 3q +3q +4q ? 4q sync pattern thresh_corr sync pattern < thresh_corr q = 2 bits = 1 quat = search location
3.0 circuit descriptions BT8954 3.3 receiver voice pair gain framer 3-8 conexant n8954dsc 3.3.4 descrambler the mc enables the descrambler by setting dscram_en bit of the receive command register and selects the descrambler algorithm via the dscram_tap [rcmd_2; 0x91.5,4]. the descrambler, if enabled, descrambles all dsl receive data except the sync word. the algorithm is chosen from one of two possible choices, depending on whether BT8954 is located at the central office or at a remote site. the descrambler is basically a 23-bit-long linear feedback shift register (lfsr). the algorithm chosen determines the feedback points. the lfsr structure and polynomials for the two descrambler algorithms are illustrated in figure 3-6 and figure 3-7 . the descrambler is clocked with bclk. figure 3-6. lfsr structure for transmission in the remote central office direction x k-1 x k-2 x k-3 x k-4 x k-5 x k-6 x k-7 x k-8 x k-15 x k-14 x k-13 x k-12 x k-11 x k-10 x k-9 x k-17 x k-18 x k-19 x k-20 x k-21 x k-22 x k-23 x k-16 unscrambled output (ck) scrambled input (b k ) polynomial: ck = xk-23 + + xk-18 b k + = modulo-2 summation (xor gate) z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 = delay element (d flip-flop clocked with bclk) + + figure 3-7. lfsr structure for transmission in the central office remote direction x k-1 x k-2 x k-3 x k-4 x k-5 x k-6 x k-7 x k-8 x k-15 x k-14 x k-13 x k-12 x k-11 x k-10 x k-9 x k-17 x k-18 x k-19 x k-20 x k-21 x k-22 x k-23 x k-16 + unscrambled output (ck) + scrambled input (b k ) z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 polynomial: ck = xk-23 + + xk-5 b k + = modulo-2 summation (xor gate) z -1 = delay element (d flip-flop clocked with bclk)
BT8954 3.0 circuit descriptions voice pair gain framer 3.3 receiver n8954dsc conexant 3-9 3.3.5 payload demux the payload demux block extracts the indicator (ind), embedded operations channel (eoc), and the s-bits from each receive frame and places them in microcomputer-accessible registers: receive indicator bits [rind 0xe2, 0xe3] receive embedded operations channel [reoc 0xe0, 0x61] receive signaling fifos [rsfifo_o; 0xe4] double-buffering is used to ensure that the oh and signaling information read by the microcomputer is not corrupted by newly arriving data. the microcomputer must read the contents of the oh registers within 6 ms for every frame; otherwise the data is overwritten with new received data. the microcomputer must read the contents of the rsfifo_o register within 6 ms, 3 ms, 2 ms, or 1 ms, depending on the extra_sig_update configuration bits that are programmed in command register 1 [cmd_1; 0xc0].
3.0 circuit descriptions BT8954 3.4 transmitter voice pair gain framer 3-10 conexant n8954dsc 3.4 transmitter the transmitter muxes payload data from the pcm channel with overhead and signaling data into serially encoded 2b1q data that is sent to the bit pump through the tdat pin. figure 3-8 details the transmitter block diagram, which consists of overhead (oh) registers, the payload mux, and the 2b1q encoder. 3.4.1 oh/signaling registers the oh/signaling registers are the s-bits, ind, eoc, crc, and sync word registers. refer to the overhead bit allocation section, table 3-1 , for the oh bit positions in the dsl transmit frame. the oh/signaling registers are accessible by the microcomputer for writing and reading. figure 3-8. transmitter block diagram scrambler sync = command register bit s-bit ind eoc payload mux 2b1q encoder tdat rdat_descr dd_loop qclk word crc pcm tfifo bclk oh/signaling registers crc reg 1 0 scram_en 1 0 4-level 1 stuff
BT8954 3.0 circuit descriptions voice pair gain framer 3.4 transmitter n8954dsc conexant 3-11 3.4.2 transmit signaling fifos using two sets of transmit signaling fifos (tsfifo_i and tsfifo_o), double buffering ensures that the mc has enough time to write new signaling information without corrupting the signaling information being transmitted, as illustrated in figure 3-9 . the mc loads the tsfifo_i registers after receiving the ld_tsig interrupt. in the default case, ld_tsig is the same as the dsl 6 ms receive frame interrupt that occurs upon the arrival of the 6 ms dsl frame. the ld_tsig interrupt can be made to occur more frequently than 6 ms by programming non-00 values in the extra_sig_update bits in the cmd_1 register [0xc0]. six, three, two, or one millisecond(s) later, tsfifo_i registers are loaded into tsfifo_o registers at the next ld_tsig. tsfifo_o, which is then transmitted, is not thereby corrupted by the new tsfifo_i values being written by the mc during the next interval. 3.4.3 payload mux the payload mux multiplexes the overhead bits from the oh registers, payload data from the pcm tfifo, the sync word and the crc bits that were calculated for the previous transmit frame. figure 3-9. double buffering, using transmit s-bits registers ld blocks in dsl frame block1 s payload block48 s payload tsfifo_o[1] tsfifo_o[48] tsfifo_o[2] block2 s payload tsfifo output regs tsfifo_i[1] tsfifo_i[48] tsfifo_i[2] tsfifo input regs ld ld ld_tsig computer ld_tsig mc loads tsfifo_i regs tsfifo_i transmit tsfifo_o regs dsl_subframe_n (6 ms, 3 ms, 2 ms, 1 ms) dsl_subframe_n+1 (6ms, 3ms, 2ms, 1ms) tsfifo_o
3.0 circuit descriptions BT8954 3.4 transmitter voice pair gain framer 3-12 conexant n8954dsc 3.4.4 crc calculation the crc calculation is performed on all transmit data, and the payload mux inserts the resulting 6-bit crc into the subsequent output frame. crc is calculated over all bits in the (n)th frame except the sync word, stuff, and crc bits and then is inserted into the (n+1) frame. the mpu can choose to inject crc errors on a per-frame basis by setting the icrc_err bit [tcmd_1; addr 0x86.1]. the six crc bits are calculated as follows: 1. all bits of the (n) frame ? except the 14 sync and 6 crc bits, for a total of m bits ? are used in order of occurrence to construct a polynomial in x such that bit 0 of the (n) frame is the coefficient of the term x m-1 and bit m-1 of the (n) frame is the coefficient of the term x 0 . 2. the polynomial is multiplied by the factor x 6 , and the result is divided, modulo 2, by the generator polynomial x 6 x 1. coefficients of the remainder polynomial are used, in order of occurrence, as an ordered set of check bits, crc1 ? crc6, for the (n+1) frame. ordering is such that the coefficient of term x 5 in the remainder polynomial is check bit crc1, and the coefficient of term x 0 is check bit crc6. 3. check bits crc1 ? crc6 contained in a frame are associated with the contents of the preceding frame. when there is no immediately preceding frame, check bits may be assigned any value. 3.4.5 scrambler the mc enables the scrambler by setting scram_en [tcmd_1; 0x86.0] and selects the descrambler algorithm via scram_tap [tcmd_2; 0x87.2]. the scrambler, if enabled, scrambles all dsl transmit data except the sync word and stuff bits. the algorithm is chosen from one of two possible choices, depending on whether BT8954 is located at the central office or at a remote site. scrambler algorithms: the scrambler is basically a 23-bit-long linear feedback shift register (lfsr). the algorithm chosen determines the feedback points. the lfsr structure and polynomials for the two scrambler algorithms are illustrated in figure 3-10 and figure 3-11 . figure 3-10. lfsr structure for transmission in the remote central office direction x k-1 x k-2 x k-3 x k-4 x k-5 x k-6 x k-7 x k-8 x k-15 x k-14 x k-13 x k-12 x k-11 x k-10 x k-9 x k-17 x k-18 x k-19 x k-20 x k-21 x k-22 x k-23 x k-16 + scrambled output (ck) + unscrambled input (b k ) z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 polynomial: ck = xk-23 + + xk-18 b k + = modulo-2 summation (xor gate) z -1 = delay element (d flip-flop clocked with bclk)
BT8954 3.0 circuit descriptions voice pair gain framer 3.4 transmitter n8954dsc conexant 3-13 3.4.6 2b1q encoder the 2b1q encoder converts the data to be transmitted to the bit pump into sign and magnitude data according to the quaternary alignment provided on the qclk input. table 3-3 depicts how sign and magnitude bits generate 2b1q coded outputs on tdat. figure 3-11. lfsr structure for transmission in the central office remote direction x k-1 x k-2 x k-3 x k-4 x k-5 x k-6 x k-7 x k-8 x k-15 x k-14 x k-13 x k-12 x k-11 x k-10 x k-9 x k-17 x k-18 x k-19 x k-20 x k-21 x k-22 x k-23 x k-16 + unscrambled output (ck) + scrambled input (b k ) z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 polynomial: ck = xk-23 + + xk-5 b k + = modulo-2 summation (xor gate) z -1 = delay element (d flip-flop clocked with bclk) table 3-3. 2b1q encoder alignment first input bit (sign) second input bit (magnitude) quaternary symbol 00 ? 3 01 ? 1 11+1 10+3
3.0 circuit descriptions BT8954 3.5 pcm formatter voice pair gain framer 3-14 conexant n8954dsc 3.5 pcm formatter the pcm formatter shifts out the pcmr data at the rising edge of pcmcki, samples the pcmt data at the falling edge of pcmcki, and generates the pcm frame sync signals based on the pcm format configuration register [0xf1] as illustrated in figure 3-12 . the pcm formatter supports direct connection to popular pcm codecs. because the formatter generates only one frame sync signal for each pcm codec, codecs like the texas instruments tp3054a that have two frame sync signals (fsx for transmit and fsr for receive) must have both frame syncs tied before being connected to the BT8954. all time slots carry clear voice or compressed voice channels depending on the compressed bit configuration in the pcm format register [0xf1.5]. only 2:1 adpcm compression is allowed. therefore, a 64 kbps time slot is carrying either 2 x 32 kbps of compressed voice or 64 kbps or clear voice. the BT8954 has a maximum capacity of 18 clear or 36 compressed voice channels. the frame syncs are in an encoded or decoded form depending on the enc_fsync bit configuration in pcm_format [0xf1.6]. if enc_fsync is reset, the pcm formatter can generate up to 18 frame syncs (pcmf[18:1]). in this case, the frame syncs of all the unused time slots are held low. for example, for a pcm4 system, pcmf[4:1] are active but pcmf[18:5] are held low. if enc_fsync is set, the pcm formatter generates the frame syncs in the encoded_frame_sync mode, driving the channel numbers through epcmf[6:1], but holding pcmf[18:7] low. externally, decoders can be used to generate frame syncs from the channel numbers. the period of pcmf[18:1] or epcmf[6:1] for clear channels is 8 times the pcmcki period, while the period for compressed channels is 4 times the pcmcki period. figure 3-12. pcm formatter detail pcm formatter pcm rfifo pcm tfifo pcm codecs pcmr pcmcko pcmf[18:1] pcmt adpcmck pcmcki
BT8954 3.0 circuit descriptions voice pair gain framer 3.5 pcm formatter n8954dsc conexant 3-15 the pcmf[18:1] (epcmf[6:1]) waveforms for various scenarios are illustrated in figure 3-13 . figure 3-13. pcmf [18:1] waveforms for encoded and decoded frame sync modes note(s): sync_width (pcm_format_4) = 0001; fsync2byte (pcm_format_4) = 0001. pcmcki 1) pcm2: 2 clear channels pcmf1 pcmf2 pcmf[18:3] pcmt/ byte1 byte2 2) pcm18: 18 clear channels pcmf1 pcmf18 pcmt/ 3) adpcm36: 18 compressed channels epcmf[6:1] pcmf[18:7] pcmt/ [00 0001] [00 0010] [00 0001] [0000 0000 0000] byte1[7:4] byte1[3:0] byte18[7:4] byte18[3:0] byte1[7:4] byte1 (2.048 mhz) 14 unused time slots [00 0011] [10 0010] [00 0000] [10 0011] [10 0100] byte2[7:4] byte17[3:0] byte1 byte2 byte17 byte18 byte1 pcmr pcmr pcmr pcmcki (2.048 mhz) pcmcki (2.048 mhz) 30 unused timeslots time slot 2 time slot 1 3.9056s 125s
3.0 circuit descriptions BT8954 3.6 loopbacks voice pair gain framer 3-16 conexant n8954dsc 3.6 loopbacks BT8954 provides multiple pcm and dsl loopbacks as illustrated in figure 3-14 . the output towards which data is looped is called the test direction. loopback activation in the test direction does not disrupt the through-data path in the non-test direction. table 3-4 lists the loopback controls which are designated by initials corresponding to test direction and the channel from which data is looped. figure 3-14. pcm and dsl loopbacks pcmr pcmt pp_loop dp_loop pcm channel pd_loop dd_loop dsl channel rdat tdat table 3-4. pcm and dsl loopbacks loopback command register test direction loopback description pp_loop cmd_1; 0xc0 receive pcm loopback on pcm side dp_loop cmd_1; 0xc0 transmit dsl loopback on pcm side pd_loop rcmd_2; 0x91 receive pcm loopback on dsl channel dd_loop tcmd_2; 0x87 transmit dsl loopback on dsl channel
BT8954 3.0 circuit descriptions voice pair gain framer 3.7 synchronization n8954dsc conexant 3-17 3.7 synchronization all signals are synchronized to tdsl_6ms, rdsl_6ms, tpcm_6ms, and rpcm_6ms. all status registers are synchronized to either tdsl_6ms or rdsl_6ms. the transmitter signals at the dsl (pcm) interface are synchronized to tdsl_6ms (tpcm_6ms). the receiver signals at the dsl (pcm) interface are synchronized to rdsl_6ms (rpcm_6ms). the main contributor to the phase differences between the dsl_6ms and pcm_6ms signals is that while data is received and transmitted in a bursty fashion at the pcm interface, it is received and transmitted in a continuous fashion at the dsl interface. the detailed relationship between the dsl_6ms and pcm_6ms signals depends on whether the framer is at the central office (cotf) or at the remote site (rtf). even though tpcm_6ms and rpcm_6ms may not be phase-aligned, tfifo and rfifo provide sufficient data buffering for pcmf to mark coincident pcm receive and transmit 125 s frame boundaries. the synchronization between cotf and rtf is illustrated in figure 3-15 . 3.7.1 cotf transmitter synchronization in the cotf, tpcm_6 ms is always a free-running 6 ms-period signal. at the central office, the dsl transmit frames are slaved to the pcm frame timing. as illustrated in figure 3-16 , tdsl_6 ms is a 6 ms-period signal that is phase-offset from tpcm_6ms by tfifo_wl.cot (tfifo water level in the cotf). tfifo_wl.cot determines the amount of pcm data written into the tfifo before the transmitter begins extracting dsl frames from the tfifo. figure 3-15. cotf and rtf synchronization transmitter.cot cot framer tpcm_6 ms tdsl_6 ms (master) (slave) receiver.cot rpcm_6 ms rdsl_6 ms (slave) (master) receiver.rt rt framer rdsl_6 ms rpcm_6 ms (master) (slave) transmitter.rt tdsl_6 ms tpcm_6 ms (slave) (master) rpcm_6 ms = tpcm_6 ms rpcm_6 ms!= tpcm_6 ms variable path delay figure 3-16. cotf transmitter synchronization tpcm_6 ms 6 ms tdsl_6 ms 6 ms tfifo_wl.cot
3.0 circuit descriptions BT8954 3.7 synchronization voice pair gain framer 3-18 conexant n8954dsc 3.7.2 rtf receiver synchronization the rdsl_6 ms signal in the rtf is generated after sync_word has been detected on rdat. as illustrated in figure 3-17 , rpcm_6 ms is phase-offset from rdsl_6ms by rfifo_wl.rt (rfifo water level in the rtf). the pcm receive frames are slaved to the dsl receive frame timing at the remote site. 3.7.3 rtf transmitter synchronization in the rtf, the rpcm_6 ms and tpcm_6 ms signals are the same because the same pcm frame sync is used for transmitting and receiving pcm frames from the pcm codecs. as illustrated in figure 3-18 , tdsl_6ms is phase-offset from tpcm_6 ms by tfifo_wl.rt (tfifo water level in the rtf). the dsl transmit frames are slaved to the pcm transmit frame timing, which in turn is slaved to the dsl receive frame timing at the remote site. tfifo_wl.rt = tfifo_wl.cot. figure 3-17. rtf receiver synchronization rfifo_wl.rt 6 ms 6 ms sync_word sync_word rdsl_6 ms rdat rpcm_6 ms figure 3-18. rtf transmitter synchronization tpcm_6 ms 6 ms tfifo_wl.rt = tfifo_wl.cot 6 ms tdsl_6 ms
BT8954 3.0 circuit descriptions voice pair gain framer 3.7 synchronization n8954dsc conexant 3-19 3.7.4 cotf receiver synchronization the rdsl_6ms signal in the cotf is generated after sync_word has been detected as illustrated in figure 3-19 . rpcm_6ms is phase-offset from rdsl_6ms by rfifo_wl.rt (rfifo water level in the rtf) plus time to realign to the next tpcm_125 s. at the central office, the pcm receive frames are slaved to the dsl frame timing and aligned to the transmit pcm_125 s frame. the re-alignment time is added because the same pcm frame sync signal is used for transmitting and receiving pcm frames from the pcm codecs. 3.7.5 round trip delay the microcomputer determines the round-trip delay by measuring the time that elapses between the tx and rx interrupts in the interrupt status register [isr; 0xd0] at the central office. figure 3-19. cotf receiver synchronization 125 s rfifo_wl.rt 6 ms 6 ms sync_word sync_word 125 s realign to tpcm_125 s rdsl_6 ms rdat rpcm_6 ms tpcm_125 s
3.0 circuit descriptions BT8954 3.8 microcomputer interface voice pair gain framer 3-20 conexant n8954dsc 3.8 microcomputer interface the microcomputer interface (mci) port ( figure 3-20 ) configures and controls operating modes, manages overhead protocol, and reads status information from BT8954. in addition, BT8954 may signal its need for attention from the microcomputer (mc) by requesting an interrupt. the port can be directly connected to common mcs like the motorola 68302 or the intel 8051. figure 3-20. mci port microcomputer microcomputer interface addr[6:0] ad[7:0] muxed ale wr/rw* cs* motel* irq* rst* ds*
BT8954 3.0 circuit descriptions voice pair gain framer 3.8 microcomputer interface n8954dsc conexant 3-21 3.8.1 microcomputer read/write the mci provides access to a 128-byte internal address space. figure 3-21 depicts the read/write controls. the mci uses either an 8-bit-wide multiplexed address-data bus (intel style) or one 8-bit-wide data bus and another separate 7-bit-wide address bus (motorola style) for external data communications. the interface is configured with the inputs, motel* and muxed. motel* low selects intel-type microcomputer and control signals: ale, cs*, rd*, wr*. motel* high selects motorola-type microcomputer and control signals: ale, cs*, ds*, r/w*. muxed high configures the interface to use the multiplexed address-data bus with both the address and data on the ad[7:0] pins. muxed low configures the interface to use separate address and data buses with the data on the ad[7:0] pins and the address on the addr[6:0] pins. 3.8.1.1 multiplexed address/data bus the timing for a read or write cycle is stated in chapter 5.0, electrical and mechanical specifications . during a read operation, an external microcomputer places an address on the address-data bus which is then latched on the falling edge of ale. data is placed on the address-data bus after cs* and rd* (or ds*) go low. the read cycle is completed with the rising edge of cs* and rd* (or ds*). a write operation latches the address from the address-data bus at the falling edge of ale. the microcomputer places data on the address-data bus after cs* and wr* (or ds*) go low. motorola mci has r/w* falling edge preceding the falling edge of cs* and ds*. the rising edge of r/w* occurs after the rising edge of cs* and ds*. data is latched on the address-data bus on the rising edge of wr* or ds*. 3.8.1.2 separated address/data bus the timing for a read or write cycle using the separated address and data buses is essentially the same as over the multiplexed bus. the one exception is that the address must be driven onto the addr[6:0] bus rather than the ad[7:0] bus. figure 3-21. functional diagram of the read and write controls motel* rd*/ds* wr*/r/w* read strobe write strobe cs* ale ad[7:0] to registers from registers address addr[7:0] muxed
3.0 circuit descriptions BT8954 3.8 microcomputer interface voice pair gain framer 3-22 conexant n8954dsc 3.8.2 interrupt request the open drain interrupt request output (irq*) indicates when a particular set of transmit, receive, or common status registers has been updated. eight maskable interrupt sources are requested on the common irq* pin: 1. tx = transmit 6 ms frame 2. tx_err = transmit channel errors or transmit hdsl frame repositioned 3. rx = receive 6 ms frame 4. rx_err = receive channel errors or framer state transition to in_sync 5. pll_err = pll error 6. ld_tsig = load transmit signaling interrupt 7. rd_rsig = read receive signaling interrupt 8. sig_fifo_err = signaling fifo error interrupt all interrupt events are edge-sensitive. tx and rx interrupts are synchronized to the dsl channel ? s 6 ms frame. the ld_tsig, rd_rsig, and sig_fifo_err occur every 1 ms, 2 ms, 3, ms, or 6 ms. the rate is dependent on the value of extra_sig_update in cmd_1. tx_err, rx_err, and pll_err occur whenever these errors are detected. the basic structure of each interrupt source is illustrated in figure 3-22 and has two associated registers: interrupt mask register [imr; 0xd1], and interrupt status register [isr; 0xd0]. a 0 in a given bit of the imr enables the corresponding interrupt. a 1 in a given bit of the imr disables the corresponding interrupt, thereby preventing it from activating irq*. by reading the isr, the mc can determine the cause of an interrupt event. active interrupts are indicated by isr bits that are read high while inactive interrupts are indicated by isr bits that are read low. writing a 0 to an interrupt status register bit [isr; 0xd0] clears the corresponding interrupt, and if no other interrupts are pending, deactivates irq*. writing a 1 to any isr bit has no effect. irq* is an open-drain output and must be tied to a pullup resistor. this allows irq* to be tied together with a common interrupt request. figure 3-22. interrupt logic interrupt data irq* mask status set write isr write imr other interrupt sources read imr read isr reset event
BT8954 3.0 circuit descriptions voice pair gain framer 3.8 microcomputer interface n8954dsc conexant 3-23 3.8.3 reset the reset input (rst*) is an active-low input that presets all imr bits and clears all interrupt enables (disabling the irq* output). the following registers are reset synchronously by the gclk to a value of 0x00: isr, rcmd_1, rcmd_2, dframe_len, sync_word, cmd_1, pframe_len, and pcm_format. this means the f pll must be programmed, and then a reset must be applied to the rst* pin. when a reset is applied to the rst* pin, the imr is asynchronously set to a value of 0xff. the following configuration of the BT8954 is not valid: num_sbits [tcmd2] = 0 extra_z_bit [cmd_1] = 1 num_chan [pcm_format1] = 0x0b dframe_len = 0x58
3.0 circuit descriptions BT8954 3.9 pll voice pair gain framer 3-24 conexant n8954dsc 3.9 pll the bit pump is the clock master of BT8954, which in turn is a clock master of the codecs. the pll synthesizes a variety of (adpcmck, pcmcko) frequency pairs from hclk (hclk is 32 times the bit clock, bclk). figure 3-23 details the pll architecture. first, hclk is scaled by 1/pll_x in the prescaler to produce f ref . the pll output frequency, f pll , is in general a non-integer multiple (pll_int.fracp) of f ref . the f pll is post-scaled by 1/pll_w to give adpcmck, which in turn is scaled by 1/pll_y to give pcmcko. the frequency of gclk, f gclk , is f pll divided by p_factor. gclk clocks all the registers in the microcomputer interface. p_factor is given by the pll_p[1:0] bits of the pll_scale register [0xb5.6:5]. when pll_p[1] = 1 and pll_p[0] = 1, then the p_factor is set to 8. when pll_p[1] = 1 and pll_p[0] = 0, then the p_factor is set to 4. when pll_p[1] = 0, then the p_factor is dependent on the value of pll_w. this allows you to adjust the value of gclk. a lower value of gclk lowers the power requirements of the device and the maximum speed of the microprocessor bus. the value for f pll is either 196.608 mhz or 204.800 mhz. figure 3-23. functional diagram of the pll note(s): legend ? f h = hclk frequency; f p = pcmcko frequency; f g = gclk frequency; f a = adpcmck frequency. f h 1/pll_x pll hclk fref = f h/pll _x f pll =pll_int.fracp x f ref adpcmck gclk 1/pll_int.fracp 1/pll_w 1/pll_y pcmcko out_of_lock core 1/p_factor
BT8954 3.0 circuit descriptions voice pair gain framer 3.9 pll n8954dsc conexant 3-25 adpcmck and pcmcko are related to bclk and hclk through the following equations: the fractional part, fracp, is scaled as follows: the out_of_lock output is the pll_err interrupt. pll_int[5:0] bits are in the pll_int register [0xb0], frac bits are in the pll_frac_hi and pll_frac_lo registers [0xb1 and 0xb2], the a bit is in the pll_a register [0xb3], and the b bit is in the pll_b register [0xb4]. pll_x is represented by the pll_x register bits of the pll_scale register [0xb5.0,1], as given in table 3-5 . table 3-5. pll_x register mapping pll_x[1] pll_x[0] f h /f ref 00 1 01 2 11 4 1 0 sleep mode f b n x 64 kbps non payloadbitrate ? + = f h 32 x f b = f ref f h pll _x ------------------ = f pll f ref x pll _ int . fracp = f adpcmck f pll pll _w ------------------- - = f pcmcko f adpcmck pll _y ------------------------- - = fracp frac () a b --- + 65536 ------------------------------ - ?? ?? ?? ?? =
3.0 circuit descriptions BT8954 3.9 pll voice pair gain framer 3-26 conexant n8954dsc pll_w and pll_y are represented by the pll_c[2:0] register bits of the pll_scale register [0xb5.4:2], as given in table 3-6 . pll_p bits are also selected in the pll_scale register to control the internal gclk frequency, as detailed in table 3-7 . table 3-6. pll_c register bit representation of pll_w and pll_y f pll pll_c[2] pll_c[1] pll_c[0] pll_w f adpcmck pll_y f pcmcko 204.800 mhz 0 0 0 10 20.480 mhz 10 2.048 mhz 196.608 mhz 0 0 0 1 1 0 24 8.192 mhz 4 2.048 mhz table 3-7. pll_p register bit representation of p_factor pll_p[1] pll_p[0] pll_w p_factor f gclk = f pll / p_factor max p freq = f gclk /2 0 0 0 0 0 0 10 24 32 5 6 4 f pll / 5 f pll / 6 f pll / 4 f pll / 10 f pll / 12 f pll / 8 0 0 0 1 1 1 10 24 32 10 12 8 f pll / 10 f pll / 12 f pll / 8 f pll / 20 f pll / 24 f pll / 16 10x4 f pll / 4 f pll / 8 11x8 f pll / 8 f pll / 16
BT8954 3.0 circuit descriptions voice pair gain framer 3.9 pll n8954dsc conexant 3-27 ideally, the voltage crystal oscillator (vco) should be operated around 200 mhz. therefore, f gclk is approximately 50 mhz. table 3-8 lists the various factors that synthesize different frequencies for f pll = 196.608 mhz. not all possible configurations are illustrated. table 3-9 lists the various factors that synthesize different frequencies for f pll = 204.800 mhz. table 3-8. factors for f pll = 196.608 mhz (1 of 2) n n x 64 (kbps) non-payload bit rate (khz) f b (khz) f h (mhz) f h /f ref f ref (mhz) int frac a/b 2 128 8 136 4.352 1 4.352 45 11565 3/17 16 144 4.608 1 4.608 42 43690 2/3 32 160 5.120 1 5.120 38 26214 2/5 40 168 5.376 1 5.376 36 37449 1/7 64 192 6.144 1 6.144 32 0 0/1 72 200 6.400 1 6.400 30 47185 23/25 4 256 8 264 8.448 1 8.448 23 17873 5/11 16 272 8.704 1 8.704 22 38550 10/17 32 288 9.216 1 9.216 21 21845 1/3 40 296 9.472 1 9.472 20 49594 30/37 64 320 10.240 1 10.240 19 13107 1/5 72 328 10.496 1 10.496 18 47953 7/41 6 384 8 392 12.544 1 12.544 15 44136 24/49 16 400 12.800 1 12.800 15 23592 24/25 32 416 13.312 1 13.312 14 50412 4/13 40 424 13.568 1 13.568 14 32149 39/53 64 448 14.336 1 14.336 13 46811 3/7 72 456 14.592 1 14.592 13 31043 7/19 8 512 8 520 16.640 1 16.640 11 53437 3/65 16 528 16.896 1 16.896 11 41704 8/11 32 544 17.408 1 17.408 11 19275 5/17 40 552 17.664 1 17.664 11 8548 4/23 64 576 18.432 1 18.432 10 43690 2/3 72 584 18.688 1 18.688 10 34114 46/73
3.0 circuit descriptions BT8954 3.9 pll voice pair gain framer 3-28 conexant n8954dsc 12 768 8 776 24.832 2 12.416 15 54725 91/97 16 784 25.088 2 12.544 15 44136 24/49 32 800 25.600 2 12.800 15 23592 24/25 40 808 25.856 2 12.928 15 13626 30/101 64 832 26.624 2 13.312 14 50412 4/13 72 840 26.880 2 13.440 14 41194 2/35 18 1152 8 1160 37.120 4 9.280 21 12203 37/145 16 1168 37.376 4 9.344 21 2693 19/73 32 1184 37.888 4 9.472 20 49594 30/37 40 1192 38.144 4 9.536 20 40465 27/149 64 1216 38.912 4 9.728 20 13797 1/19 72 1224 39.168 4 9.792 20 5140 4/51 table 3-8. factors for f pll = 196.608 mhz (2 of 2) n n x 64 (kbps) non-payload bit rate (khz) f b (khz) f h (mhz) f h /f ref f ref (mhz) int frac a/b table 3-9. factors for f pll = 204.800 mhz (1 of 2) n n x 64 (kbps) non-payload bit rate (khz) f b (khz) f h (mhz) f h /f ref f ref (mhz) int frac a/b 2 128 8 136 4.352 1 4.352 47 3855 1/17 16 144 4.608 1 4.608 44 29127 1/9 32 160 5.120 1 5.120 40 0 0/1 40 168 5.376 1 5.376 38 6241 11/21 64 192 6.144 1 6.144 33 21845 1/3 72 200 6.400 1 6.400 32 0 0/1 4 256 8 264 8.448 1 8.448 24 15887 17/33 16 272 8.704 1 8.704 23 34695 9/17 32 288 9.216 1 9.216 22 14563 5/9 40 296 9.472 1 9.472 21 40738 22/37 64 320 10.240 1 10.240 20 0 0/1 72 328 10.496 1 10.496 19 33567 9/41
BT8954 3.0 circuit descriptions voice pair gain framer 3.9 pll n8954dsc conexant 3-29 6 384 8 392 12.544 1 12.544 16 21399 25/49 16 400 12.800 1 12.800 16 0 0/1 32 416 13.312 1 13.312 15 25206 2/13 40 424 13.568 1 13.568 15 6182 34/53 64 448 14.336 1 14.336 14 18724 4/7 72 456 14.592 1 14.592 14 2299 29/57 8 512 8 520 16.640 1 16.640 12 20164 60/65 16 528 16.896 1 16.896 12 7943 25/33 32 544 17.408 1 17.408 11 50115 13/17 40 552 17.664 1 17.664 11 38941 47/69 64 576 18.432 1 18.432 11 7281 7/9 72 584 18.688 1 18.688 10 62842 54/73 12 768 8 776 24.832 2 12.416 16 32430 18/97 16 784 25.088 2 12.544 16 21399 25/49 32 800 25.600 2 12.800 16 0 0/1 40 808 25.856 2 12.928 15 55154 6/101 64 832 26.624 2 13.312 15 25206 2/13 72 840 26.880 2 13.440 15 15603 17/21 18 1152 8 1160 37.120 4 9.280 22 4519 21/29 16 1168 37.376 4 9.344 21 60149 35/73 32 1184 37.888 4 9.472 21 40738 22/37 40 1192 38.144 4 9.536 21 31228 84/149 64 1216 38.912 4 9.728 21 3449 5/19 72 1224 39.168 4 9.792 20 59967 89/153 table 3-9. factors for f pll = 204.800 mhz (2 of 2) n n x 64 (kbps) non-payload bit rate (khz) f b (khz) f h (mhz) f h /f ref f ref (mhz) int frac a/b
3.0 circuit descriptions BT8954 3.9 pll voice pair gain framer 3-30 conexant n8954dsc
n8954dsc conexant 4-1 4 4.0 registers for registers that contain less than 8 bits, assigned bits reside in lsb positions, unassigned bits are ignored during write cycles, and are indeterminate during read cycles. the lsb in all registers is bit position 0. all registers are randomly accessible. all register values written can be read back except where noted. 4.1 register types the mc must read and write real-time registers (receive and transmit eoc, ind, s-bit, and status registers), within a prescribed time interval (1 ? 6 ms) after the dsl channel ? s 6 ms frame interrupt to avoid reading or writing transitory data values. failure to read real-time registers within the prescribed interval results in a loss of data. the mc writes to non-real-time command registers are event-driven and occur when the system initializes, changes modes, or responds to an error condition. the mc reads can be interrupt-event driven, polled, or a combination of both, allowing the choice to be dictated by system architecture. polled procedures can avoid reading transitory real-time data by monitoring the interrupt status register bits [isr; 0xd0] to determine when a particular group of registers has been updated. interrupt-driven and polled procedures must complete reading within the prescribed 1 ? 6 ms interval following dsl frame interrupts. 4.2 register groups BT8954 command, status, and real-time registers are divided into three groups: transmit receive common the group of transmit and receive registers only affects operation or reports status of the dsl channel. transmit registers reference data flow from the pcm channel to the dsl channel output. receive registers reference data flow from the dsl channel to the pcm channel outputs. common registers affect overall operation, primarily the pcm channel and the pll.
4.0 registers BT8954 4.3 address map voice pair gain framer 4-2 conexant n8954dsc 4.3 address map table 4-1 provides the address map. table 4-1. address map (1 of 2) address (hex) acronym description 0x80 teoc_lo transmit embedded operations channel low 0x81 teoc_hi transmit embedded operations channel high 0x82 tind_lo transmit indicator bits low 0x83 tind_hi transmit indicators bits high 0x84 tsfifo_i, tsfifo_o transmit signaling fifos 0x85 tfifo_wl transmit fifo water level 0x86 tcmd_1 transmit command register 1 0x87 tcmd_2 transmit command register 2 0x90 rcmd_1 receive command register 1 0x91 rcmd_2 receive command register 2 0xa0 dframe_len dsl frame length 0xa1 sync_word sync word 0xa2 rfifo_wl_lo rx fifo water level low 0xa3 rfifo_wl_hi rx fifo water level high 0xb0 pll_int pll_int 0xb1 pll_frac_hi pll_frac_hi 0xb2 pll_frac_lo pll_frac_lo 0xb3 pll_a pll_a 0xb4 pll_b pll_b 0xb5 pll_scale pll_scale 0xc0 cmd_1 command register 1 0xc1 rev_id revision identification 0xd0 isr interrupt status register 0xd1 imr interrupt mask register 0xd3 scr_rst scrambler reset 0xd4 tfifo_rst transmit fifo reset 0xd5 tsfifo_ptr_rst reset pointer to transmit signaling fifos 0xd6 rsfifo_ptr_rst reset pointer to receive signaling fifos
BT8954 4.0 registers voice pair gain framer 4.3 address map n8954dsc conexant 4-3 0xd7 rfifo_rst receive elastic store fifo reset 0xd8 sync_rst receive framer synchronization reset 0xd9 err_rst error count reset 0xda rx_rst reset receiver 0xdb update_tsfifo_0 update tsfifo_0 0xdc update_rsfifo_0 update rsfifo_0 0xe0 reoc_lo receive embedded operations channel low 0xe1 reoc_hi receive embedded operations channel high 0xe2 rind_lo receive indicator bits low 0xe3 rind_hi receive indicator bits high 0xe4 rsfifo_i, rsfifo_o receive signaling fifos 0xe5 rstatus_1 receive status 1 0xe6 rstatus_2 receive status 2 0xe7 tstatus_1 transmit status 1 0xe8 crc_cnt crc error count 0xe9 febe_cnt far end block error count 0xf0 frame_len pcm frame length 0xf1 pcm_format pcm format table 4-1. address map (2 of 2) address (hex) acronym description
4.0 registers BT8954 4.4 transmitter registers voice pair gain framer 4-4 conexant n8954dsc 4.4 transmitter registers transmitter registers are summarized in table 4-2 . 0x80, 0x81?transmit embedded operations channel (teoc_lo, teoc_hi) the transmit embedded operations channel (eoc) holds 13 eoc bits for transmission in the next frame. refer to table 3-1 on page 3-3 for the eoc bit positions within the frame. the payload mux samples teoc coincident with the dsl channel ? s transmit 6 ms frame interrupt. unmodified registers repeatedly output their contents in each frame. the most significant bit, teoc[12], is transmitted first. teoc_lo (address 0x80) teoc_hi (address 0x81) 0x82, 0x83?transmit indicator bits (tind_lo, tind_hi) transmit indicator (ind) holds 13 ind bits for transmission in the next frame and includes the febe bit, tind[1]. refer to table 3-1 on page 3-3 for the ind bit positions within the frame. the payload mux samples tind coincident with the dsl channel ? s transmit 6 ms frame interrupt. unmodified registers repeatedly output their contents in each frame. the most significant bit, tind[12], is transmitted first. note: BT8954 does not automatically output febe. proper transmit of febe requires the mc to copy the crc_err bit from rstatus_2 [0xe6] to tind[1]. table 4-2. transmitter register summary address register label bits name/description 0x80 teoc_lo 8 transmit embedded operations channel 0x81 teoc_hi 5 transmit embedded operations channel 0x82 tind_lo 8 transmit indicator 0x83 tind_hi 5 transmit indicator 0x84 tsfifo_i, tsfifo_o 48 x 8 transmit signaling fifos 0x85 tfifo_wl 8 tfifo water level 0x86 tcmd_1 6 transmit command register 1 0x87 tcmd_2 8 transmit command register 2 7 6 5 4 3 2 1 0 teoc[7:0] 15 14 13 12 11 10 9 8 ? ? ? teoc[12:8]
BT8954 4.0 registers voice pair gain framer 4.4 transmitter registers n8954dsc conexant 4-5 tind_lo (address 0x82) tind_hi (address 0x83) 0x84 ? transmit signaling fifos (tsfifo_i, tsfifo_o) tsfifo_i[48:1], tsfifo_o[48:1] employing a double-buffering scheme, two 48-byte fifos (transmit signaling input fifo [tsfifo_i] and transmit signaling output fifo [tsfifo_0]), transmit signaling information, as illustrated in figure 4-1 . 7 6 5 4 3 2 1 0 tind[7:0] 15 14 13 12 11 10 9 8 ??? tind[12:8] figure 4-1. transmit signaling fifos note(s): (1) from mc; for testing only tsfifo_i[48] tsfifo_i[2] tsfifo_i[1] tsfifo_o[48] tsfifo_o[2] tsfifo_o[1] ld_tsig from mc io test_tsfifo (from transmitter) update_tsfifo_o (1) to transmitter to m c (1)
4.0 registers BT8954 4.4 transmitter registers voice pair gain framer 4-6 conexant n8954dsc the number of signaling bits is set in tcmd_2 address [0x87]. the msb of the signaling bits is always in the msb of the tsfifo. an example of three signaling bits is illustrated in figure 4-2 . up to 48 bytes of transmit signaling information can be loaded into tsfifo_i by the mc after it receives the load transmit signaling interrupt (ld_tsig) from the transmitter. the mc has 6 ms, 3 ms, 2 ms, or 1 ms, (depending on the extra_sig_update configuration in the cmd_1 register [0xc0.4:3] from the current ld_tsig to the next ld_tsig to load 48, 24, 16, or 8 tsfifo_i entries. tsfifo_i is loaded into tsfifo_o at every ld_tsig interrupt before tsfifo_i is modified by the mc. mc access to tsfifo_i is provided by first writing to tsfifo_ptr_rst [0xd5] to reset the write pointer, and then writing up to 48 entries sequentially. tsfifo_i[1] is written first. BT8954 increments the tsfifo_i write pointer after each write cycle to the tsfifos address. the pointer wraps around to point to the first entry (tsfifo_i[1]) after the 48th entry (tsfifo_i[48]) has been written. therefore, the tsfifo_i write pointer needs to be reset only once (that is, during initialization) if 48 entries are written every 6 ms. for testing purposes, mc read access to tsfifo_o is provided by first writing to tsfifo_ptr_rst [0xd5] to reset the tsfifo_o read pointer, and then reading up to 48 entries sequentially. tsfifo_o[1] is read first. BT8954 increments the tsfifo_o read pointer after each read access to the tsfifos address. the pointer wraps around to point to the first entry (tsfifo_o[1]) after the 48th entry (tsfifo_o[48]) has been read. also, for testing, writing any value to the update_tsfifo_o address [0xdb] initiates copying tsfifo_i into tsfifo_o, provided the test_tsfifo bit in tcmd_1 [0x86] is set. 0x85 ? transmit fifo water level (tfifo_wl) transmit fifo water level contains the number of bclk cycles to delay from the pcm 6 ms frame to the start of the dsl transmit sync word. a value of zero equals 1 bclk delay. figure 4-2. example of three signaling bits tsfifo msb lsb 12 3 x x x x x 12 3 x x x x x msb lsb rsfifo 7 6 5 4 3 2 1 0 tfifo_wl[7:0]
BT8954 4.0 registers voice pair gain framer 4.4 transmitter registers n8954dsc conexant 4-7 0x86 ? transmit command register 1 (tcmd_1) real-time commands (bits 0 ? 5) are sampled by the oh multiplexer on the respective transmit frame to affect operation in the next outgoing frame. doh_en and force_one command bit combinations provide the transmit data encoding options needed to perform standard dsl channel start-up procedures. test_tsfifo test transmit signaling fifo ? enables the copying of tsfifo_i into tsfifo_o by the mc, so that the tsfifos can be tested from the mc. 0 = disable testing of tsfifos; enable normal operation 1 = enable testing of tsfifos; disable normal operation force_one force all 1s payload ? transmit payload data bytes are replaced by all 1s. force_one and scram-en are set, and doh_en is cleared to enable output of a 4-level framed scrambled 1s signal. 0 = normal payload transmission 1 = force 4-level 1s payload doh_en dsl overhead enable ? the oh multiplexer inserts eoc, ind, and crc bits. otherwise, transmit overhead bits, except sync word, are forced to 4-level 1s. 0 = oh transmitted as 4-level 1s 1 = normal oh transmission icrc_err inject crc error ? logically inverts the 6 calculated crc bits in the next frame. 0 = normal crc transmission 1 = transmit errored crc scram_en scrambler enable ? all transmit dsl channel bits, except sync word bits, are scrambled per the scr_tap setting in tcmd_2 [0x87]. otherwise, transmit data passes through the scrambler unchanged. 0 = scrambler bypassed 1 = scrambler enabled 7 6 5 4 3 2 1 0 ?? ? test_tsfifo force_one doh_en icrc_err scram_en
4.0 registers BT8954 4.4 transmitter registers voice pair gain framer 4-8 conexant n8954dsc 0x87 ? transmit command register 2 (tcmd_2) en_auto_tfifo _rst enable automatic tfifo_rst ? when set, the tfifo is reset the instant that the receive framer changes state from sync_acquired to in_sync. 0 = tfifo not automatically reset by sync_acquired in_sync 1 = tfifo automatically reset by sync_acquired in_sync repeat_en enable repeater mode ? when set, dsl frames received on rdat are re-transmitted with new overhead after bypassing all the fifos. 0 = normal transmit 1 = repeater mode num_sbits[3:0] number of valid s-bits in each tsfifo and rsfifo register ? 0 = no s-bits transmitted or received 1 8 = 1 8 valid s-bits in each tsfifo and rsfifo register scram_tap scrambler tap ? selects which delay stage, 5th or 18th, to tap for feedback in the transmit scrambler. the system ? s dsl terminal type dictates which scrambler tap should be selected. 0 = htu-c or ltu terminal type, scrambler taps 5th delay stage 1 = htu-r or ntu terminal type, scrambler taps 18th delay stage for the repeater (figure 2): 0 = BT8954 (c r), scrambler tapes 5th delay stage 1 = BT8954 (r c), scrambler tapes 18th delay stage dd_loop loopback to dsl on the dsl side ? receive dsl data (rdat) is switched to transmit dsl data (tdat) to accomplish a loopback of the dsl channel on the dsl side. loopback data is switched at i/o pins and does not alter dsl receive operations. if the dscram_en [rcmd_2; 0x91.5] and scam_en [tcmd_1; 0x86.0] bits are set, rdat is switched to tdat after descrambling and scrambling. 0 = normal transmit 1 = t dat s u p p l i e d by r dat p i n 7 6 5 4 3 2 1 0 en_auto_ tfifo_rst repeat_en num_sbits[3:0] scram_tap dd_loop
BT8954 4.0 registers voice pair gain framer 4.5 receiver registers n8954dsc conexant 4-9 4.5 receiver registers one group of registers configures the receiver and controls the mapping of dsl payload bytes into the receiver elastic store (rfifo). the configuration register defines the dsl receive framer ? s criteria for loss and recovery of frame alignment by selecting the number of detected sync word errors used to declare loss of sync or needed to acquire sync. refer to figure 3-4, receive framer finite state machine on page 3-6 the dsl write registers are listed in table 4-3 . frame alignment criteria are programmable to meet different standard application requirements. 0x90 ? receive command register 1 (rcmd_1) en_auto_rfifo _rst enable automatic rfifo_rst- ? when set, the rfifo is reset at the instant that the receive framer changes state from the sync_acquired to the in_sync state. 0 = rfifo not automatically reset by sync_acquired in_sync 1 = rfifo automatically reset by sync_acquired in_sync framer_en receive framer enable ? instructs the receive framer to search for the sync word pattern programmed in sync_word [0xa1]. when disabled, the framer does not count errors or generate interrupts. table 4-3. dsl receive write registers address register label bits name/description 0x90 rcmd_1 8 configuration 0x91 rcmd_2 8 configuration 7 6 5 4 3 2 1 0 en_auto_ rfifo_rst framer_en loss_sync[2:0] reach_sync[2:0] framer_en receive framer search 0 disabled; framer forced to out_of_sync 1 enabled; search for sync_word
4.0 registers BT8954 4.5 receiver registers voice pair gain framer 4-10 conexant n8954dsc loss_sync[2:0] loss of sync framing criteria ? contains the number of consecutive dsl frames in which the sync word is not detected before the receive framer moves from the in_sync to the out_of_sync state. loss_sync determines the number of sync_errored intermediate states the framer must pass through during loss of frame sync. etsi standard criteria require six consecutive frames without sync word detected. reach_sync[2:0] reach sync framing criteria ? contain the number of consecutive dsl frames in which the sync word is detected before the receive framer moves from the out_of_sync to the in_sync state. reach_sync determines the number of sync_acquired intermediate states the framer must pass through during recovery of frame sync. etsi standard criteria require two consecutive frames containing sync. 0x91 ? receive command register 2 (rcmd_2) test_rsfifo test receive signaling fifo ? enables the copying of rsfifo_i into rsfifo_o, and write access to rsfifo_i by the mc. setting this bit enables the testing of the rsfifos from the mc. 0 = disabled testing of rsfifos; enabled normal operation 1 = enabled testing of rsfifos; disabled normal operation pd_loop loopback to pcm on dsl side ? transmit dsl data (tdat) is connected back toward the pcm interface to accomplish a loopback of the pcm channel on the dsl side. receive dsl data (rdat) is ignored, but dsl transmit continues without interruption. pd_loop requires the descrambler and scrambler to use the same tap, as opposed to their normal opposing tap selection. 0 = normal receive 1 = rdat supplied by tdat loss_sync out_of_sync criteria 000 1 frame not containing sync 001 2 consecutive frames 010 3 consecutive frames 011 4 consecutive frames 100 5 consecutive frames 101 6 consecutive frames 110 7 consecutive frames 111 8 consecutive frames reach_sync in_sync criteria 000 1 frame containing sync 001 2 consecutive frames 010 3 consecutive frames 011 4 consecutive frames 100 5 consecutive frames 101 6 consecutive frames 110 7 consecutive frames 111 8 consecutive frames 7 6 5 4 3 2 1 0 test_rsfifo pd_loop dscram_en dscram_tap thresh_corr[3:0]
BT8954 4.0 registers voice pair gain framer 4.5 receiver registers n8954dsc conexant 4-11 dscram_en descrambler enable ? when enabled, all receive dsl channel data, except sync word bits, are descrambled per the dscram_tap setting. otherwise the data passes through the descrambler unchanged. 0 = descrambler bypassed 1 = descrambler enabled dscram_tap descrambler tap ? selects which delay stage, 5th or 18th, to tap for feedback in the descrambler. the system ? s terminal type dictates which tap should be selected. 0 = htu-c or ltu terminal type, descrambler selects tap 18 1 = htu-r or ntu terminal type, descrambler selects tap 5 for the repeater (figure 2): 0 = BT8954 (r c), scrambler taps 5th delay stage 1 = BT8954 (c r), scrambler taps 18th delay stage thresh_corr[3:0] sync threshold correlation ? upon the receive framer ? s entry to a sync_errored state, the number of sync word locations searched is determined by the result of previous states ? threshold correlation. during an in_sync state, the framer searches the two most probable sync word locations at 6 ms 1 quat, corresponding to 0 or 4 stuff bits. one of the two locations searched must correctly match the entire 14-bit sync word or else the framer enters a sync_errored state. the highest number of matching bits found among the search locations is compared to the selected thresh_corr value to determine if the framer should expand the number of search locations. if the highest number of matching bits meets or exceeds the threshold, but wasn ? t a complete match, the framer progresses to the next sync_errored state and continues to each of the two most probable locations. otherwise, the framer progresses to the next sync_errored state, increments the number of locations to be searched, and examines quats on either side of the prior search locations. for example, if the location with highest number of matching bits is below the threshold during in_sync, then the framer enters the first sync_errored state and searches from the prior location at 6 ms 2 quats, and at 6 ms exactly. the effect of threshold correlation on the number of search locations is depicted in figure 3-5 on page 3-7. thresh_corr sync threshold correlation 1010 10 or more out of 14 bits 1011 11 or more out of 14 bits 1100 12 or more out of 14 bits 1101 13 or more out of 14 bits 1110 14 out of 14 bits
4.0 registers BT8954 4.6 dsl channel configuration voice pair gain framer 4-12 conexant n8954dsc 4.6 dsl channel configuration the dsl channel configuration write registers are listed in table 4-4 . 0xa0 ? dsl frame length (dframe_len) dframe_len[7:0] dsl frame length ? contains the number of bclk bits (less 1), in the range of 8 to 152, that are transmitted and received in a dsl payload block. each payload block consists of an integer number of 8-bit bytes (1 byte per voice channel) plus a variable number of s-bits (0 ? 8) plus 0 or 1 extra_z_bit. therefore, dframe_len = #voice channels x 8 + #s-bits, ? 1 if extra_z_bit (cmd_1; addr 0xc0) = 0 but dframe_len = voice channels x 8 + sbits if extra_z_bit = 1. 0xa1 ? sync word (sync_word) sync_word[6:0] sync_word ? holds the 7 sign bits of the 7-quat (14-bit) transmit and receive sync word. transmit sync word magnitude bits are forced to 0. sync_word[0] is the sign bit of the first transmit quat. sign precedes magnitude on the transmit data (tdat) output. the receive framer searches dsl data (rdat) for patterns matching sync_word. 0 = negative sign bit 1 = positive sign bit table 4-4. dsl channel configuration write register address register label bits name/description 0xa0 dframe_len 8 dsl frame length 0xa1 sync_word 7 sync word (sign only) 0xa2 rfifo_wl_lo 8 rx fifo water level 0xa3 rfifo_wl_hi 1 rx fifo water level 7 6 5 4 3 2 1 0 dframe_len[7:0] 7 6 5 4 3 2 1 0 ? sync_word[6:0]
BT8954 4.0 registers voice pair gain framer 4.6 dsl channel configuration n8954dsc conexant 4-13 0xa2, 0xa3 ? rx fifo water level (rfifo_wl_lo, rfifo_wl_hi) receive fifo water level sets the bclk bit delay from the master dsl channel ? s receive 6 ms frame to the pcm receive 6 ms frame. the delay is programmed in bclk bit intervals, in the range of 1 to 1024 bits. a value of 0 equals 1 bclk bit delay. rfifo_wl_lo (address 0xa2) rfifo_wl_hi (address 0xa3) 7 6 5 4 3 2 1 0 rfifo_wl[7:0] 15 14 13 12 11 10 9 8 ?????? rfifo_wl[9] rfifo_wl[8]
4.0 registers BT8954 4.7 pll configuration voice pair gain framer 4-14 conexant n8954dsc 4.7 pll configuration the pll synthesizes the pcm clock output (pcmcko) and the adpcm clock (adpcmck) from the dsl hclk (hclk = 32 x bclk). refer to tables 3-5 through 3-9 on pages 3-25 through 3-28 for the register values to load into these registers for different bclk, pcmclk, and adpcmck frequencies. a list of pll configuration write registers is displayed in table 4-5 . 0xb0 ? pll_int register (pll_int) the pll_int register contains the integer part of the f pll /f ref ratio. 0xb1 ? pll_frac_hi register (pll_frac_hi) the pll_frac_hi register contains the 8 most significant bits of the pll_frac scaled fraction. for the definition of pll_frac, see pll in section 3, circuit descriptions . 0xb2 ? pll_frac_lo register (pll_frac_lo) the pll_frac_lo register contains the 8 least significant bits of the pll_frac scaled fraction. for the definition of pll_frac, see pll in section 3, circuit descriptions . table 4-5. pll configuration write registers address register label bits name/description 0xb0 pll_int 6 pll_int register 0xb1 pll_frac_hi 8 msb of pll_frac 0xb2 pll_frac_lo 8 lsb of pll_frac 0xb3 pll_a 8 pll_a register 0xb4 pll_b 8 pll_b register 0xb5 pll_scale 7 pll_x and pll_c for pre-scaling and post-scaling 7 6 5 4 3 2 1 0 ?? pll_int[5:0] 7 6 5 4 3 2 1 0 pll__frac_hi[7:0] 7 6 5 4 3 2 1 0 pll__frac_lo[7:0]
BT8954 4.0 registers voice pair gain framer 4.7 pll configuration n8954dsc conexant 4-15 0xb3 ? pll_a register (pll_a) the pll_a register contains the a part of scaling pll_fracp. for the definitions of pll_a and pll_fracp, see pll in section 3, circuit descriptions . 0xb4 ? pll_b register (pll_b) the pll_b register contains the b part of scaling pll_fracp. for the definitions of pll_b and pll_fracp, see pll in section 3, circuit descriptions . 0xb5 ? pll_scale register (pll_scale) the pll_scale register contains the pll_x and pll_c values for pre-scaling the pll input and for post-scaling the pll output. pll_p indicates the maximum microcomputer frequency the BT8954 supports ( f gclk /2) . for the definitions of pll_c, pll_x, and pll_p, see pll in section 3, circuit descriptions . 7 6 5 4 3 2 1 0 pll_a[7:0] 7 6 5 4 3 2 1 0 pll_b[7:0] 7 6 5 4 3 2 1 0 ? pll_p[1:0] pll_c[2:0] pll_x[1] pll_x[0]
4.0 registers BT8954 4.8 common voice pair gain framer 4-16 conexant n8954dsc 4.8 common common command write registers are listed in table 4-6 . 0xc0 ? command register 1 (cmd_1) pcmn_range indicates range for pcmn. 0 = pcm_8 pcm18 (i.e., for pcm_format1 register: 8 < num_chan < 18) 1 = pcm1 pcm7 (1) (i.e., for pcm_format1 register: 1 < num_chan < 7) note: use pcmn_range = 0 for pcm7 with 8 signaling bits (since pcm7 with 8 signaling bits is equivalent to pcm8 with 0 signaling bits). extra_z_bit if set, enables the transmit of an extra 8 kbps z-bit field in the dsl frame. 0 = basic dsl frame structure transmit 1 = transmit extra z-bit in each block of the dsl frame table 4-6. common command write registers address register label bits name/description 0xc0 cmd_1 7 command 0xc1 rev_id 3 revision id 7 6 5 4 3 2 1 0 ? pcmn_range extra_z_bit extra_sig_update[1:0] dp_loop pp_loop sync_slave
BT8954 4.0 registers voice pair gain framer 4.8 common n8954dsc conexant 4-17 extra_sig_ update[1:0] number of extra ld_tsig/rd_rsig signaling interrupts per 6 ms dsl frame in addition to the normal signaling interrupt that occurs coincident with the dsl frame boundary. 00 = default case: no extra signaling interrupt. corresponds to one signaling interrupt every 6 ms, coincident with the dsl frame boundary. 01 = one extra signaling interrupt. corresponds to two signaling interrupts every 6 ms, or one signaling interrupt every 3 ms. that is, one occurs coincident with the dsl frame boundary, and the other occurs 3 ms (or 24 payload blocks) later. 10 = two extra signaling interrupts. corresponds to three signaling interrupts every 6 ms. that is, one signaling interrupt every 2 ms: one occurs coincident with the dsl frame boundary, and the other two signaling interrupts occur 2 ms (or 16 payload blocks) and 4 ms (or 32 payload blocks) later. 11 = five extra signaling interrupts. corresponds to six signaling interrupts every 6 ms. that is, one signaling interrupt every 1 ms: one occurs coincident with the dsl frame boundary, and the other five signaling interrupts occur 1 ms (or 8 payload blocks), 2 ms (or 16 payload blocks), 3 ms (24 payload blocks), 4 ms (or 32 payload blocks), and 5 ms (or 40 payload blocks) later. dp_loop loopback towards dsl on the pcm side ? the pcmt input is replaced by data generated from the receiver. the receiver operates normally, but the transmit pcmt is ignored. 0 = normal pcm transmit operation 1 = transmit pcm data supplied by the receiver pp_loop loopback towards pcm on the pcm side ? the pcmr output is connected from the pcmt input. signals are switched directly at the i/o pins. dsl transmit and receive channels operate normally, except the receive channel outputs are replaced by loopback signals. 0 = normal pcm receive 1 = pcmr is supplied by pcm transmit input sync_slave pcm syncs slaved to the dsl receives sync when set to 1. 0 = pcm sync master 1 = receive dsl sync master 0xc1 ? revision identification (rev_id) ver[2:0] ve r s i o n n u m b e r ? contains the device revision level which the mc can read to determine the installed device. 000 = BT8954 rev a 001 = BT8954 rev b 010 = BT8954 rev c 7 6 5 4 3 2 1 0 ?? ? ?? ver[2:0]
4.0 registers BT8954 4.9 interrupt voice pair gain framer 4-18 conexant n8954dsc 4.9 interrupt the interrupt registers are listed in table 4-7 . 0xd0 ? interrupt status register (isr) the interrupt status register (isr) consists of independent read/write interrupt flags, one for each of eight internal sources. each flag bit is set and stays set when its corresponding source indicates that a valid interrupt event occurred (for edge-triggered interrupts) or a valid interrupt condition exists (for level-sensitive interrupts). if unmasked, this event causes the irq* output to be activated. writing a logic 0 to an interrupt flag causes the flag to be immediately cleared. attempting to clear a flag whose underlying condition still exists does not immediately clear the flag, but allows it to remain set until the underlying condition expires, at which time the flag is cleared automatically. the clearing of an unmasked flag causes the irq* output to return to an inactive state, if no other unmasked interrupt flags are set. sig_fifo_err signaling fifo error interrupt ? informs the mc that a signaling fifo error has occurred (tsfifo_i_over or tsfifo_i_under or tsififo_o_over or tsfifo_o_under or rsfifo_i_over or rsfifo_i_under or rsfifo_o_over or rsfifo_o_under). 0 = no interrupt 1 = sig_fifo_err interrupt rd_rsig read receive signaling interrupt ? instructs the mc to read new receive signaling information before the next rd_rsig interrupt occurs. this interrupt occurs every 6 ms, 3 ms, 2 ms, or 1 ms depending on the extra_sig_update configuration in the cmd_1 register [0xc0]. a rd_rsig interrupt always occurs coincident with the start of the receive dsl 6 ms frame, i.e., whenever an rx interrupt occurs. 0 = no interrupt 1 = rd_rsig interrupt ld_tsig load transmit signaling interrupt ? instructs the mc to load new transmit signaling information before the next ld_tsig interrupt occurs. this interrupt occurs every 6 ms, 3 ms, 2 ms, or 1 ms depending on the extra_sig_update configuration in the cmd_1 register [0xc0]. a ld_tsig interrupt always occurs coincident with the start of the transmit dsl 6 ms frame, i.e., whenever a tx interrupt occurs. 0 = no interrupt 1 = ld_tsig interrupt table 4-7. interrupt registers address register label bits name/description 0xd0 isr 8 interrupt status register 0xd1 imr 8 interrupt mask register 7 6 5 4 3 2 1 0 sig_fifo_err rd_rsig ld_tsig pll_err rx_err rx tx_err tx
BT8954 4.0 registers voice pair gain framer 4.9 interrupt n8954dsc conexant 4-19 pll_err pll error interrupt ? indicates if pll is in an out-of-lock state. 0 = pll in-lock 1 = pll out-of-lock rx_err receive error interrupt ? framer state transition to out_of sync, rfifo errors; crc and febe counter overflows are logically ored to form rx_err. 0 = no interrupt 1 = receive error interrupt rx receive dsl 6 ms frame interrupt ? reported coincident with the start of the receive dsl 6 ms frame. this allows the mc to synchronize read access of the receive status registers. 0 = no interrupt 1 = receive frame interrupt tx_err transmit error interrupt ? generated whenever the transmit hdsl frame is repositioned or a tfifo underflow/overflow error occurs. 0 = no interrupt 1 = transmit error interrupt/transmit hdsl frame repositioned tx transmit dsl 6 ms frame interrupt ? reported coincident with the start of the transmit dsl 6 ms frame. this allows the mc to synchronize read access of the transmit status [tstatus_1; 0xe7] and write access to the real-time transmit dsl registers. 0 = no interrupt 1 = transmit frame interrupt 0xd1 ? interrupt mask register (imr) the interrupt mask register (imr) consists of independent read/write mask bits for each isr [0xd0] interrupt flag. a logic 1 represents the masked condition, a logic 0 the unmasked condition. all mask bits behave identically with respect to their corresponding interrupt flags. setting a mask bit prevents the corresponding interrupt flag from affecting the irq* output. clearing a mask allows the interrupt flag to affect irq* output. unmasking an active interrupt flag immediately causes the irq* output to go active, if currently inactive. masking an active interrupt flag causes irq* to go inactive, if no other unmasked interrupt flags are set. upon rst* assertion, all imr bits are automatically set to 1 to disable the irq* output. sig_fifo_err mask the sig_fifo_err interrupt. rd_rsig mask the rd_rsig interrupt. ld_tsig mask the ld_tsig interrupt. pll_err mask the pll error interrupt. rx_err mask the dsl receive error interrupt. rx mask the dsl 6 ms receive frame interrupt. tx_err mask the dsl transmit error interrupt. tx mask the dsl 6 ms transmit frame interrupt. 7 6 5 4 3 2 1 0 sig_fifo_err rd_rsig ld_tsig pll_err rx_err rx tx_err tx
4.0 registers BT8954 4.10 reset voice pair gain framer 4-20 conexant n8954dsc 4.10 reset the reset write registers are listed in table 4-8 . 0xd3 ? scrambler reset (scr_rst) writing any data value to scr_rst sets the 23 stages of the scrambler lfsr to 0x000001. scr_rst is used during conexant production test to verify scrambler operation and is not required during normal operation. 0xd4 ? transmit fifo reset (tfifo_rst) writing any data value to tfifo_rst empties the tfifo. the mc must write tfifo_rst whenever the tfifo reports an overflow or underflow [tstatus_1; 0xe7], and after the pll has settled. each write to tfifo_rst may cause up to three tfifo errors to be reported in subsequent dsl frames. therefore, the mc must ignore up to three tfifo errors reported after writing the tfifo_rst command. 0xd5 ? reset pointer to transmit signaling fifos (tsfifo_ptr_rst) writing any data value to tsfifo_ptr_rst resets the pointer to the transmit signaling input fifos. 0xd6 ? reset pointer to receive signaling fifos (rsfifo_ptr_rst) writing any data value to rsfifo_ptr_rst resets the pointers to the receive signaling fifos. table 4-8. reset write registers address register label name/description 0xd3 scr_rst scrambler reset 0xd4 tfifo_rst transmit fifo reset 0xd5 tsfifo_ptr_rst tsfifo pointer reset 0xd6 rsfifo_ptr_rst rsfifo pointer reset 0xd7 rfifo_rst receive fifo reset 0xd8 sync_rst receive framer synchronization reset 0xd9 err_rst error count reset 0xda rx_rst reset receiver 0xdb update_tsfifo_o update tsfifo_o 0xdc update_rsfifo update rsfifo_o
BT8954 4.0 registers voice pair gain framer 4.10 reset n8954dsc conexant 4-21 0xd7 ? receive elastic store fifo reset (rfifo_rst) writing any data value to rfifo_rst empties the rfifo and forces the payload mapper to realign dsl bytes with respect to the receive dsl 6 ms frame. the mc must write rfifo_rst whenever an rfifo error is reported [rstatus_1; 0xe5], and after the pll has settled. writing rfifo_rst corrupts up to three receive pcm frames worth of data. 0xd8 ? receive framer synchronization reset (sync_rst) writing any data value to sync_rst forces the receive framer to the out_of_sync state, which restarts the sync word search and causes the framer to issue an rx_err interrupt [isr; 0xd0.3]. the mc must write sync_rst after modifying framer_en [rcmd_1; 0x90.6], or sync_word. writing sync_rst corrupts up to three receive pcm frames worth of data. 0xd9 ? error count reset (err_rst) writing any data value to err_rst clears the receive crc error counter [crc_cnt; 0xe8], the receive far end block error counter [febe_cnt; 0x6e9] and consequently clears the counter overflow crc_ovr and febe_ovr bits [rstatus_2; 0xe6.6:7]. err_rst clears the error counters immediately and must be issued within 6 ms after the respective receive frame interrupt in order to avoid clearing unreported errors. no other receive errors (crc_err or rfifo) are affected by err_rst. 0xda ? reset receiver (rx_rst) writing any data value to rx_rst forces the pcm formatter to align the pcm receive timebase with respect to the dsl channel ? s receive 6 ms frame by reloading the rfifo_wl value [0xa2, 0xa3]. the mc must write rx_rst after modifying the rfifo_wl value. BT8954 automatically performs rx_rst each time the receive framer changes alignment and transitions to the in_sync state, if the en_auto_rfifo_rst is set. issuing rx_rst while the pcm formatter is aligned causes no change in alignment of the pcm receive timebase. 0xdb ? update tsfifo_o (update_tsfifo_o) writing any data value to update_tsfifo_o initiates a copy of tsfifo_i into tsfifo_o. this is only used for testing. 0xdc ? update rsfifo_o (update_rsfifo_o) writing any data value to update_rsfifo_o initiates a copy of rsfifo_i into rsfifo_o. this is only used for testing.
4.0 registers BT8954 4.11 receive/transmit status voice pair gain framer 4-22 conexant n8954dsc 4.11 receive/transmit status the mc can read all receive and transmit status registers non-destructively at any time. all status registers are updated coincident with the dsl channel ? s receive or transmit 6 ms frame interrupts indicated in the interrupt status register [isr; 0xd0]. therefore, the mc can poll the isr or enable interrupts to determine if a status update has occurred. real-time receive status (reoc, rind, and rsbit) register updates are suspended when the receive framer reports an out_of_sync state [rstatus_2; 0xe6]. the receive and transmit status read registers are listed in table 4-9. 0xe0, 0xe1 ? receive embedded operations channel (reoc_lo, reoc_hi) receive eoc holds 13 eoc bits received during the previous dsl frame. refer to table 3-1 on page 3-3 for eoc bit positions within the frame. the most significant bit, reoc[12] is received first. reoc_lo (address 0xe0) reoc_hi (address 0xe1) 0xe2, 0xe3 ? receive indicator bits (rind_lo, rind_hi) receive ind holds 13 ind bits received during the previous dsl frame. refer to table 3-1 on page 3-3 for the ind bit positions within the frame. the receive framer updates the rind registers on receive frame interrupt boundaries. the most significant bit rind[12] is received first. table 4-9. receive and transmit status read registers address register label bits register description 0xe0 reoc_lo 8 receive eoc bits 0xe1 reoc_hi 5 receive eoc bits 0xe2 rind_lo 8 receive ind bits 0xe3 rind_hi 5 receive ind bits 0xe4 rsfifo_i, rsfifo_o 48 x 8, 48 x 8 receive signaling fifos 0xe5 rstatus_1 8 receive status 1 0xe6 rstatus_2 8 receive status 2 0xe7 tstatus_1 8 transmit status 0xe8 crc_cnt 8 crc error count 0xe9 febe_cnt 8 far end block error count 7 6 5 4 3 2 1 0 reoc[7:0] 15 14 13 12 11 10 9 8 ??? reoc[12:8]
BT8954 4.0 registers voice pair gain framer 4.11 receive/transmit status n8954dsc conexant 4-23 rind_lo (address 0xe2) rind_hi (address 0xe3) 0xe4 ? receive signaling fifos (rsfifos) rsfifo_i[48:1], and rsfifo_o[48:1] employing a double-buffering scheme, two 48-byte fifos, receive signaling input fifo (rsfifo_i), and receive signaling output fifo (rsfifo_o) are used to receive signaling information, as illustrated in figure 4-3 . 7 6 5 4 3 2 1 0 rind[7:0] 15 14 13 12 11 10 9 8 ??? rind[12:8] figure 4-3. receive signaling fifos note(s): (1) from receiver (2) from mc; for testing only (3) for testing only rsfifo_0[48] rsfifo_0[2] rsfifo_0[1] rsfifo_i[48] rsfifo_i[2] rsfifo_i[1] update_rsfifo_o (2) to i o rd_rsig (1) from mc (3) test_rsfifo mc o i v test_rs fifo v from receiver out_of_sync
4.0 registers BT8954 4.11 receive/transmit status voice pair gain framer 4-24 conexant n8954dsc the number of signaling bits is set in tcm2_2 address [0x87]. the lsb of the signaling bits is always in the lsb of the rsfifo, as illustrated in figure 4-4 . up to 48 bytes of receive signaling information are loaded into rsfifo_i by the receiver after every rd_rsig interrupt, provided that the framer is not in an out_of_sync state. rsfifo_i[1] is received first. up to 48 bytes of receive signaling information can be read from rsfifo_o by the mc after it receives the rd_rsig interrupt. the mc has 6 ms, 3 ms, 2 ms, or 1 ms (depending on the extra_sig_update configuration in the cmd_1 register [0x3c0.3:4]) from the current rd_rsig to the next rd_rsig to read 48, 24, 16, or 8 rsfifo_o entries. rsfifo_i is loaded into rsfifo_o at every rd_rsig interrupt, before rsfifo_i is modified by the receiver. mc access to rsfifo_o is provided by first writing to rsfifo_ptr_rst [0xc6] to reset the read pointer, and then reading up to 48 entries sequentially. rsfifo_o[1] is read first. BT8954 increments the rsfifo_o read pointer after read cycle. the pointer wraps around to point to first entry (rsfifo_o[1]) after the 48th entry (rsfifo_o[48]) has been read. therefore, the rsfifo_o read pointer needs to be reset only once (that is, during initialization) if 48 entries are read every 6 ms. for testing purposes, mc write access to rsfifo_i is provided by first writing to rsfifo_ptr_rst [0xc6] to reset the rsfifo_i write pointer, and then writing up to 48 entries sequentially. rsfifo_i[1] is written first. BT8954 increments the rsfifo_i write pointer after each write access to the rsfifo ? s address. the pointer wraps around to point to the first entry (rsfifo_i[1]) after the 48th entry (rsfifo_i[48]) has been written. also, for testing, writing any value to the update_rsfifo_o register [0xdc] initiates copying rsfifo_i into rsfifo_o, provided the test_rsfifo bit in rcmd_2 [0x91] is set. 0xe5 ? receive status 1 (rstatus_1) tr_invert tip/ring inversion ? indicates the receive framer acquired an inverted sync word a or b, indicating the receive tip and ring wire pair connections are reversed. BT8954 automatically inverts the sign bits of all received data as it is presented on the rdat input when inversion is detected. tr_invert is updated each time the receive framer state transitions from out_of_sync to sync_acquired. 0 = sync_acquired with expected sync word 1 = sync_acquired with inverted sync word figure 4-4. example of three signaling bits tsfifo msb lsb 12 3 x x x x x 12 3 x x x x x msb lsb rsfifo 7 6 5 4 3 2 1 0 ? tr_invert rsfifo_o_ under rsfifo_o_ over rsfifo_i_ under rsfifo_i_over rfifo_under rfifo_over
BT8954 4.0 registers voice pair gain framer 4.11 receive/transmit status n8954dsc conexant 4-25 rsfifo_o_under receive signaling input fifo_under error ? indicates that rsfifo_o has underflowed. that is, rsfifo_o is being read by the mc faster than it is being updated with rsfifo_i. also reported in isr (as part of sig_fifo_err) and generates a sig_fifo_err interrupt (if sig_fifo_err in imr is enabled). 0 = rsfifo_o normal 1 = rsfifo_o underflowed rsfifo_o_over receive signaling input fifo_over error ? indicates that rsfifo_o has overflowed. that is, rsfifo_o is being updated faster than read by the mc. also reported in isr (as part of sig_fifo_err) and generates a sig_fifo_err interrupt (if sig_fifo_err in imr is enabled). 0 = rsfifo_o normal 1 = rsfifo_o overflowed rsfifo_i_under receive signaling input fifo_under error ? indicates that rsfifo_i has underflowed. that is, rsfifo_i is being copied into rsfio_o faster than it is being updated (from receive dsl frames). also reported in isr (as part of sig_fifo_err) and generates a sig_fifo_err interrupt (if sig_fifo_err in imr is enabled). rsfifo_i_under cannot be permanently cleared. writing any value to rsfifo_ptr_rst [0x06] can temporarily clear this error. on the next rd-rsig interrupt, rsfifo_i_under is again set. 0 = rsfifo_i normal 1 = rsfifo_i underflowed rsfifo_i_over receive signaling input fifo_over error ? indicates that rsfifo_i has overflowed. that is, rsfifo_i is being updated faster (from receive dsl frames) than it is being copied into rsfifo_o. also reported in isr (as part of sig_fifo_err) and generates a sig_fifo_err interrupt (if sig_fifo_err in imr is enabled). 0 = rsfifo_i normal 1 = rsfifo_i overflowed rfifo_under receive fifo_under error ? indicates the rfifo has underrun. also reported in isr and generates an rx_err interrupt (if rx_err in imr is enabled). rfifo_under is indicative of clock problems and may be triggered by events similar to those which cause rfifo_over errors. 0 = rfifo normal 1 = rfifo underrun rfifo_over receive fifo_over error ? indicates the rfifo has overflowed. also reported in isr and generates an rx_err interrupt (if rx_err in imr is enabled). rfifo_over is indicative of clock problems. 0 = rfifo normal 1 = rfifo overflowed
4.0 registers BT8954 4.11 receive/transmit status voice pair gain framer 4-26 conexant n8954dsc 0xe6 ? receive status 2 (rstatus_2) febe_ovr far end block error count overflow ? indicates the febe count [febe_cnt; 0x69] has reached its maximum value of 255. generates an rx_err interrupt. 0 = febe count below maximum 1 = febe count equals maximum 255 (0xff) crc_ovr crc error count overflow ? indicates the crc error count [crc_cnt; 0xe8] has reached its maximum value of 255, and generates an rx_err interrupt. 0 = crc error count below maximum 1 = crc error count equals maximum 255 (0xff) crc_err crc error ? shows that the crc comparison in the previous frame resulted in a mismatch of one or more crc bits. crc_err is invalid in the out_of_sync state. the mpu can copy crc_err into the first transmit ind [tind_lo; 0x82] to report febe. 0 = crc pass 1 = crc error detected sync_state[1:0] receive framer synchronization state ? reports the state of the receive framer. refer to figure 3-4 on page 3-6. when the framer enters out_of_sync, the rfifo is automatically reset, febe and crc error counts are suspended, and rx_err is activated. when the framer reports sync_acquired, the rfifo and the payload mapper are enabled, and rx_err is activated. when the framer enters in_sync, the rfifo water level [rfifo_wl; 0xa2, 0xa3] is re-established, febe and crc counting resumes, and rx_err is activated. when the framer reports sync_errored, state_cnt indicates the number of consecutive frames in which sync was not detected. state_cnt[2:0] intermediate state count ? applicable only if sync_state reports sync_acquired or sync_errored states. state_cnt indicates the framer ? s progress through the intermediate states. 7 6 5 4 3 2 1 0 febe_ovr crc_ovr crc_err sync_state[1:0] state_cnt[2:0] 00 out_of_sync 01 sync_acquired 10 in_sync 11 sync_errored 000 1 frame 001 2 consecutive frames 010 3 consecutive frames 011 4 consecutive frames 100 5 consecutive frames 101 6 consecutive frames 110 7 consecutive frames 111 8 consecutive frames
BT8954 4.0 registers voice pair gain framer 4.11 receive/transmit status n8954dsc conexant 4-27 0xe7 ? transmit status 1 (tstatus_1) tsfifo_o_under transmit signaling output fifo_under error ? indicates that the tsfifo_o has underflowed. that is, tsfifo_o is being read into dsl frames faster than it is being updated with tsfifo_i. also reported in isr (as part of sig_fifo_err), this error generates a sig_fifo_err interrupt (if sig_fifo_err in imr is enabled). 0 = tsfifo_o normal 1 = tsfifo_o underflowed tsfifo_o_over transmit signaling output fifo_over error indicates that tsfifo_o has overflowed. that is, the tsfifo_o is being updated faster than it is being read and transmitted in dsl frames. also, reported in isr (as part of sig_fifo_err), this error generates a sig_fifo_err interrupt (if sig_fifo_err in imr is enabled). 0 = tsfifo_o normal 1 = tsfifo_o overflowed tsfifo_i_under transmit signaling input fifo_under error ? indicates that the tsfifo_i has underflowed. that is, tsfifo_i is being copied into tsfifo_o faster than it is being updated by the mc. also reported in isr (as part of sig_fifo_err), this error generates a sig_fifo_err interrupt (if sig_fifo_err in imr is enabled). 0 = tsfifo_i normal 1 = tsfifo_i underflowed tsfifo_i_over transmit signaling input fifo_over error ? indicates that the tsfifo_i has overflowed. that is, the tsfifo_i is being updated faster by the mc than it is being copied into tsfifo_o. also reported in isr (as part of sig_fifo_err), this error generates a sig_fifo_err interrupt (if sig_fifo_err in imr is enabled). 0 = tsfifo_i normal 1 = tsfifo_i overflowed tfifo_under transmit fifo_under error ? indicates the tfifo has underrun. also reported in isr, this error generates a tx_err interrupt (if tx_err in imr is enabled). 0 = tfifo normal 1 = tfifo underrun tfifo_over transmit fifo_over error ? indicates the tfifo has overflowed. also reported in isr, this error generates a tx_err interrupt (if tx_err in imr is enabled). 0 = tfifo normal 1 = tfifo overflowed 7 6 5 4 3 2 1 0 ?? tsfifo_o_ under tsfifo_o_ over tsfifo_i_under tsfifo_i_over tfifo_under tfifo_over
4.0 registers BT8954 4.12 pcm formatter voice pair gain framer 4-28 conexant n8954dsc 0xe8 ? crc error count (crc_cnt) crc_cnt[7:0] crc error count ? indicates the total number of received crc errors detected by the receive framer and increments by one for each received dsl 6 ms frame that contains crc_err [rstatus_2; 0xe6]. crc_cnt is cleared to 0 by err_rst [0xd9], and error counting is suspended while the receive framer is out_of_sync or sync_acquired. crc_cnt also sets crc_ovr [rstatus_2; 0xe6] upon reaching its maximum count value of 255. 0xe9 ? far end block error count (febe_cnt) febe_cnt[7:0] far end block error count ? indicates the total number of received febe errors sent by the far end transmitter and increments by one for each received dsl 6 ms frame that contains an active (low) febe bit. febe is the second ind bit received within the indicator bit group and can be monitored separately as the rind[1] bit in the rind_lo [0xe2] receive status register. refer to the dsl frame format subsection, table 2, for the febe bit position within the frame. febe_cnt is reset to 0 by err_rst [0xd9], and error counting is suspended while the receive framer is out_of_sync or sync_acquired. febe_cnt also sets febe_ovr [rstatus_2; 0xe6] upon reaching its maximum count value of 255. 4.12 pcm formatter the pcm formatter registers are listed in table 4-10 . 7 6 5 4 3 2 1 0 crc_cnt[7:0] 7 6 5 4 3 2 1 0 febe_cnt[7:0] table 4-10. pcm formatter register summary address register label bits register description 0xf0 pframe_len 8 pcm frame length 0xf1 pcm_format 8 pcm format
BT8954 4.0 registers voice pair gain framer 4.12 pcm formatter n8954dsc conexant 4-29 0xf0 ? pcm frame length (pframe_len) pframe_len[7:0] pcm frame length contains the number of bits in one 125 s pcm frame less 1. the selected value is given by 8 x (# time slots in 125 s pcm frame) ? 1 if pcm_freq (pcm_format1; addr 0xf1) = 0, pframe_len = 8 x 32 ? 1 = 255 if pcm_freq (pcm_format1; 0xf1) = 1, pframe_len = 8 x 24 ? 1 = 191 0xf1 ? pcm format (pcm_format1) pcm_freq pcmcki frequency. 0 : f pcmcki = 2.048 mhz 1 : f pcmcki = 1.536 mhz enc_fsync indicates if pcmf[6:1] contains encoded pcm frame syncs. if enc_fsync is 1, pcmf[6:1] is encoded. 0 = pcmf[6:1] is decoded 1 = encoded pcmf[6:1] enc_fsync must be programmed as 1 if the number of compressed voice channels exceeds 18, the total number of available pcmf pins. for example, if num_chan = 10 and compressed = 1, enc_fsync must be 1, since 20 (the number of pcmf strobes needed to represent 20 compressed voice channels) is greater than 18, which is the number of available pcmf pins. compressed indicates if each time slot carries one 64 kbps clear voice channel or carries two 32 kbps compressed voice channels. 0 = all channels are clear 1 = all channels are compressed num_chan[4:0] number of used pcm time slots. satisfies the following inequality: 1 <= num_chan[4:0] <= 18 7 6 5 4 3 2 1 0 pframe_len[7:0] 7 6 5 4 3 2 1 0 pcm_freq enc_fsync compressed num_chan[4:0]
4.0 registers BT8954 4.12 pcm formatter voice pair gain framer 4-30 conexant n8954dsc
n8954dsc conexant 5-1 5 5.0 electrical and mechanical specifications 5.1 electrical specifications 5.1.1 absolute maximum ratings the absolute maximum ratings are listed in table 5-1 . 5.1.2 recommended operating conditions the recommended operating conditions are listed in table 5-2 . table 5-1. absolute maximum ratings symbol parameter minimum maximum units vdd supply voltage ? 0.3 7 v v i voltage on any signal pin ? 1.0 vdd+0.3 v t st storage temperature ? 40 125 c t vsol vapor phase soldering temperature (1 minute) ? 220 c j a thermal resistance (68 plcc), still air ? 39.8 c / w note(s): stresses greater than those listed in this table may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 5-2. recommended operating conditions symbol parameter minimum maximum units vdd supply voltage 4.75 5.25 v t amb ambient operating temperature ? 40 85 c v ih high-level input voltage 2.0 vdd+0.3 v v i l low-level input voltage for tck@ 25 c low-level input voltage for all other inputs -0.3 -0.3 0.4 0.8 v v
5.0 electrical and mechanical specifications BT8954 5.1 electrical specifications voice pair gain framer 5-2 conexant n8954dsc 5.1.3 electrical characteristics the electrical characteristics are listed in table 5-3 . 5.1.4 dsl interface timing the qclk timing requirements are displayed in table 5-4 . qclk timing and dsl interface timing are illustrated in figures 5-1 and 5-2 . table 5-3. electrical characteristics symbol parameter minimum maximum units i dd supply current @ f gclk = 25 mhz supply current @ f gclk = 33 mhz supply current @ f gclk = 50 mhz ? 55 70 100 ma ma ma v oh high-level output voltage @ i oh = ? 200 ua 2.4 ? v v ol low-level output voltage @ i ol = 2 ma low-level irq* output voltage @ i od = 1.0 ma ? 0.4 0.4 v v i pr resistive pullup current 40 500 a i i input leakage current ? 10 10 a i oz three-state leakage current ? 10 10 a c in input capacitance ? 2.5 pf c ld output capacitive loading ? 70 pf c z high-impedance output capacitance ? 85 pf table 5-4. qclk timing requirements symbol parameter minimum maximum units 1 qclk frequency 0.080 0.584 mhz 2 clock width high tqclk/2 ? 20 tqclk/2 + 20 ns 3 clock width low tqclk/2 ? 20 tqclk/2 + 20 ns figure 5-1. qclk timing qclk 1 3 2
BT8954 5.0 electrical and mechanical specifications voice pair gain framer 5.1 electrical specifications n8954dsc conexant 5-3 table 5-5. dsl interface switching characteristics symbol parameter minimum maximum units 4 tdat setup prior to bclk falling edge 100 ? ns 5 tdat hold after bclk low 25 ? ns 6 bclk period t qclk 2t qclk 2 ? 7 bclk pulse-width high t qclk 4 ? 20 t qclk 4 + 20 ns 8 bclk pulse-width low t qclk 4 ? 20 t qclk 4 + 20 ns 9 rdat, qclk hold after bclk rising edge ? 50 ? ns 10 rdat, qclk delay after bclk high ? 50 ns figure 5-2. dsl interface timing bclk tdat qclk rdat 6 7 8 10 9 45
5.0 electrical and mechanical specifications BT8954 5.1 electrical specifications voice pair gain framer 5-4 conexant n8954dsc 5.1.5 pcm interface timing pcm interface switching characteristics are displayed in table 5-6 . pcm interface timing is illustrated in figure 5-3 . table 5-6. pcm interface switching characteristics symbol parameter minimum maximum units 11 pcmclk frequency 1.536 2.048 mhz 12 pcmclk rise time ? 50 ns 13 pcmclk fall time ? 50 ns 14 setup time, pcmfn high before pcmclk falling edge 50 ? ns 15 hold time, pcmfn high after pcmclk falling edge 50 ? ns 16 delay time, pcmclk high to pcmt data valid 0 140 ns 17 setup time, pcmr valid before pcmclk falling edge 50 ? ns 18 hold time, pcmr valid after pcmclk falling edge if gclk = 33 mhz ? hold time, pcmr valid after pcmclk falling edge if gclk = 50 mhz ? hold time, pcmr valid after pcmclk falling edge 30.4 18.5 50 50 ns ns 19 delay time, pcmclk low to pcmt data disabled 50 165 ns figure 5-3. pcm interface timing pcmclk pcmt pcmr pcmfn (short 1234567 8 frame sync) 12345678 1 pcmfn+1 (short frame sync) transmit and receive bytes for codec n 1 12 15 14 16 13 17 11 19 18 18
BT8954 5.0 electrical and mechanical specifications voice pair gain framer 5.1 electrical specifications n8954dsc conexant 5-5 5.1.6 microcomputer interface timing microcomputer interface timing and switching requirements are displayed in tables 5-6 and 5-7. mci write timing, intel mode (motel = 0) is illustrated in figure 5-4 . mci write timing, motorola mode (motel = 1) is illustrated in figure 5-5 . mci read timing, intel mode (motel = 0) is illustrated in figure 5-6 . mci read timing, motorola mode (motel = 1) is illustrated in figure 5-7 . internal write timing is illustrated in figure 5-8 . table 5-7. microcomputer interface timing requirements symbol parameter minimum maximum units 20 ale pulse-width high 30 ? ns 21 address setup prior to ale falling edge 15 ? ns 22 address hold after ale low 5 ? ns 23 ale low prior to write strobe falling edge (1) 20 ? ns 24 write strobe pulse-width low (1) 40 ? ns 25 read strobe pulse-width low (2) 50 ? ns 26 data in setup prior to write strobe rising edge (1) 30 ? ns 27 data in hold after write strobe high (1) 5 ? ns 28 r/w* setup prior to read/write strobe falling edge 10 ? ns 29 r/w* hold after read*/write strobe* high 10 ? ns 30 ale falling edge after write strobe* high 20 ? ns 31 ale falling edge after read strobe* high 20 ? ns 32 rst* pulse-width low 50 ? ns note(s): (1) in intel mode, write strobe* is defined as (wr* or cs*). in motorola mode, it is defined as (ds or cs ) when r/w is low. (2) in intel mode, read strobe* is defined as (rd* or cs). in motorola mode, it is defined as (ds or cs ) when r/w is high.
5.0 electrical and mechanical specifications BT8954 5.1 electrical specifications voice pair gain framer 5-6 conexant n8954dsc table 5-8. microcomputer interface switching characteristics symbol parameter minimum maximum units 33 data out enable (low z) after read strobe* falling edge (1) 2 ? ns 34 data out valid after read strobe* low (1) ? 50 ns 35 data out hold after read strobe* rising edge (1) 2 ? ns 36 data out disable (high z) after read strobe* high (1) ? 25 ns 37 irq* hold after write strobe* rising edge (2,3) 5 ? ns 38 irq* delay after write strobe* high (2,3) ? t qclk 32 + 20 ns 39 internal register delay after write strobe* high (3) ? t qclk 32 ? 40 internal ram delay after write strobe* high (3) ? 2 x t qclk ? 41 access data register delay after write strobe* high (3) ? 2 x t qclk ? note(s): (1) read strobe* is defined as rd* or cs* in intel mode, and ds* or cs* when r/w* is high in motorola mode. (2) when writing an interrupt mask or status register. (3) write strobe* is defined as wr* or cs* in intel mode, and ds* or cs* when r/w* is low in motorola mode. figure 5-4. mci write timing, intel mode (motel = 0) ad[7:0] write strobe* ale address data (input) 21 26 27 23 24 30 20 22
BT8954 5.0 electrical and mechanical specifications voice pair gain framer 5.1 electrical specifications n8954dsc conexant 5-7 figure 5-5. mci write timing, motorola mode (motel = 1) ad[7:0] write strobe* ale r/w* address data (input) 21 30 22 20 28 29 24 23 26 27 figure 5-6. mci read timing, intel mode (motel = 0) ad[7:0] read strobe* ale address data (output) 22 23 31 25 21 20 22 21 20
5.0 electrical and mechanical specifications BT8954 5.1 electrical specifications voice pair gain framer 5-8 conexant n8954dsc figure 5-7. mci read timing, motorola mode (motel = 1) ad[7:0] read strobe* ale address data (output) r/w* 21 35 36 34 22 33 25 31 28 20 29 figure 5-8. internal write timing irq* write strobe* internal register internal ram access data register 37 38 39 40 41
BT8954 5.0 electrical and mechanical specifications voice pair gain framer 5.1 electrical specifications n8954dsc conexant 5-9 5.1.7 test and diagnostic interface timing test and diagnostic interface timing and switching requirements are displayed in tables 5-8 and 5-9. jtag interface timing is illustrated in figure 5-9 . m table 5-9. test and diagnostic interface timing requirements symbol parameter minimum maximum units 42 tck pulse-width high 80 ? ns 43 tck pulse-width low 80 ? ns 44 tms, tdi setup prior to tck rising edge (1) 20 ? ns 45 tms, tdi hold after tck high (1) 20 ? ns note(s): (1) also applies to functional inputs for sample/preload and extest instructions. table 5-10. test and diagnostic interface switching characteristics symbol parameter minimum maximum units 46 tdo hold after tck falling edge (1) 0 ? ns 47 tdo delay after tck low (1) ? 50 ns 48 tdo enable (low z) after tck falling edge (1) 2 ? ns 49 tdo disable (high z) after tck low (1) ? 25 ns note(s): the test and diagnostic interface of the BT8954 has not yet been fully characterized; therefore, it it not being tested according to the vih, vil, voh, and vol parameters as listed. this interface is for testing only. figure 5-9. jtag interface timing tdo tck tdi tms 48 42 47 49 43 46 44 45
5.0 electrical and mechanical specifications BT8954 5.1 electrical specifications voice pair gain framer 5-10 conexant n8954dsc the input waveforms are illustrated in figure 5-10 . output waveforms are illustrated in figure 5-11 and figure 5-12 . figure 5-10. input waveforms for timing tests 3 v 0 v 2.0 v 0.8 v input high input low input high input low figure 5-11. output waveforms for timing tests vdd 0 v 2.4 v 0.4 v output high output low output high output low figure 5-12. output waveforms for three-state enable and disable tests 1.7 v 1.3 v output disabled output enabled 1.5 v v oh - 0.2 v v ol + 0.2 v output disabled
BT8954 5.0 electrical and mechanical specifications voice pair gain framer 5.2 mechanical specifications n8954dsc conexant 5-11 5.2 mechanical specifications the 68-pin plcc package is illustrated in figure 5-13 . figure 5-13. 68-pin plcc package drawing
5.0 electrical and mechanical specifications BT8954 5.2 mechanical specifications voice pair gain framer 5-12 conexant n8954dsc
n8954dsc conexant a-1 a appendix a: applications this chapter shows typical interconnections of the BT8954 voice pair gain framer to the following devices: bt8960 mdsl transceiver or bt8970 hdsl transceiver texas instrument tp3054a pcm codec motorola 68302 16-bit processor intel 8051 8-bit processor a.1 interfacing to the bt8960/bt8970 hdsl transceiver a typical interconnection between the BT8954 and the bt8960/bt8970 is illustrated in figure a-1 . figure a-1. BT8954 to bt8960/bt8970 dsl transceiver interconnection note: when low, the loop quat clock (qclk) qualifies the sign bit on the loop receive data (rdat). bt8960/bt8970 rq[1]/rdat rq[0]/bclk qclk tq[1]/tdat rdat bclk qclk tdat BT8954 tq[0] vdd 100 ?
appendix a : applications BT8954 a.2 interfacing to the texas instrument tp3054a pcm codec voice pair gain framer a-2 conexant n8954dsc a.2 interfacing to the texas instrument tp3054a pcm codec a typical interconnection between the BT8954 and the texas instrument tp3054a pcm codec is illustrated in figure a-2 . figure a-2. BT8954 to texas instrument tp3054a pcm codec interconnection pcmclk pcmfn pcmt pcmr tp3054a mclkx bclkx fsr dx dr mclkr/pdn BT8954 fsx bclkr/clksel
BT8954 appendix a : applications voice pair gain framer a.3 interfacing to the motorola 68302 16-bit processor n8954dsc conexant a-3 a.3 interfacing to the motorola 68302 16-bit processor a typical interconnection between the BT8954 and the motorola 68302 processor is illustrated in figure a-3 . figure a-3. BT8954 to motorola 68302 processor interconnection a[15] as* ds* r/w* a[6:0] d[7:0] irq6* motel* cs* ale rd* wr*/r/w* addr[6:0] irq* BT8954 mc68302 vdd dtack* muxed ad[7:0] vdd
appendix a : applications BT8954 a.4 interfacing to the intel 8051 8-bit voice pair gain framer a-4 conexant n8954dsc a.4 interfacing to the intel 8051 8-bit a typical interconnection between the BT8954 and the intel 8051 controller is illustrated in figure a-4 . a.5 references applicable specifications are listed here: bellcore ta-nwt-001210 bellcore fa-nwt-001211 etsi rtr/tm ? 03036 itu ? t recommendation g.704 bellcore tr-nwt-000499 figure a-4. BT8954 to intel 8051 controller interconnection 8051 BT8954 ad[15] ale wr rd ad[7:0] int0 motel* cs* ale wr* rd* ad[7:0] irq* vdd muxed vdd

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